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| author | Artyom Skrobov <Artyom.Skrobov@arm.com> | 2017-02-14 14:44:01 +0000 |
|---|---|---|
| committer | Artyom Skrobov <Artyom.Skrobov@arm.com> | 2017-02-14 14:44:01 +0000 |
| commit | dc66a82dc7fefbc59296de379e67497c232cd72a (patch) | |
| tree | 38cfee4f1c544ecf694fe0b9debe4fc7d6bfcd9a /llvm/lib/CodeGen | |
| parent | 9f61feac4ad389647b98305b48a3dd26caa68e07 (diff) | |
| download | bcm5719-llvm-dc66a82dc7fefbc59296de379e67497c232cd72a.tar.gz bcm5719-llvm-dc66a82dc7fefbc59296de379e67497c232cd72a.zip | |
Removing a redundant assignment
llvm-svn: 295055
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 4a9042cfb3f..e85d1951e3a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -235,7 +235,6 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node, if (II.OpInfo[i].isOptionalDef()) { // Optional def must be a physical register. - unsigned NumResults = CountResults(Node); VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); MIB.addReg(VRBase, RegState::Define); |
