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| author | Pirama Arumuga Nainar <pirama@google.com> | 2016-03-24 14:06:03 +0000 |
|---|---|---|
| committer | Pirama Arumuga Nainar <pirama@google.com> | 2016-03-24 14:06:03 +0000 |
| commit | dc45aef2d89ceb486a81ace7e7c84b0d704e56c2 (patch) | |
| tree | 72e22c134f396db685abfb8a93d2b1ee6dcf39bc /llvm/lib/CodeGen | |
| parent | 733ea34f38d0c545f46e2d891a88f2677614912d (diff) | |
| download | bcm5719-llvm-dc45aef2d89ceb486a81ace7e7c84b0d704e56c2.tar.gz bcm5719-llvm-dc45aef2d89ceb486a81ace7e7c84b0d704e56c2.zip | |
Remove unsafe AssertZext after promoting result of FP_TO_FP16
Summary:
Some target lowerings of FP_TO_FP16, for instance ARM's vcvtb.f16.f32
instruction, do not guarantee that the top 16 bits are zeroed out.
Remove the unsafe AssertZext and add tests to exercise this.
Reviewers: jmolloy, sbaranga, kristof.beyls, aadg
Subscribers: llvm-commits, srhines, aemerson
Differential Revision: http://reviews.llvm.org/D18426
llvm-svn: 264285
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 5804dfeb57f..22ab8497f4c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -436,10 +436,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) { EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); SDLoc dl(N); - SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); - - return DAG.getNode(ISD::AssertZext, dl, - NVT, Res, DAG.getValueType(N->getValueType(0))); + return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0)); } SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { |
