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authorSagar Thakur <sagar.thakur@imgtec.com>2015-08-07 06:39:38 +0000
committerSagar Thakur <sagar.thakur@imgtec.com>2015-08-07 06:39:38 +0000
commitd754890047807170f5ee6252a4024109552b4ec0 (patch)
treeea9250747e708ab16633de20177749c81f4c2e55 /llvm/lib/CodeGen
parent07d3b62548ed8c7d4686f92a69ce51d0c7050175 (diff)
downloadbcm5719-llvm-d754890047807170f5ee6252a4024109552b4ec0.tar.gz
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[LLDB][MIPS] Fix offsets of all register sets and add MSA regset and FRE=1 mode support
This change : - Fixes offsets of all register sets for Mips. - Adds MSA register set and FRE=1 mode support for FP register set. - Separates lldb register numbers and register infos of freebsd/mips64 from linux/mips64. - Re-orders the register numbers of all kinds for mips to be consistent with freebsd order of register numbers. - Eliminates ENABLE_128_BIT_SUPPORT and union ValueData from Scalar.cpp and uses llvm::APInt and llvm::APFloat for all integer and floating point types. Reviewers : emaste, jaydeep, clayborg Subscribers : emaste, mohit.bhakkad, nitesh.jain, bhushan Differential : http://reviews.llvm.org/D10919 llvm-svn: 244308
Diffstat (limited to 'llvm/lib/CodeGen')
0 files changed, 0 insertions, 0 deletions
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