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| author | Michael Berg <michael_c_berg@apple.com> | 2019-04-18 18:48:57 +0000 |
|---|---|---|
| committer | Michael Berg <michael_c_berg@apple.com> | 2019-04-18 18:48:57 +0000 |
| commit | d573aa0156b6aaf0e3cff13958f80d7c227cd656 (patch) | |
| tree | 88ee4dd1f94f87e206d8685db3f2ce8dd6e71802 /llvm/lib/CodeGen | |
| parent | ea3364bf85ef72001b8db3c6fd2dc34f9311b111 (diff) | |
| download | bcm5719-llvm-d573aa0156b6aaf0e3cff13958f80d7c227cd656.tar.gz bcm5719-llvm-d573aa0156b6aaf0e3cff13958f80d7c227cd656.zip | |
[NFC] FMF propagation for GlobalIsel
llvm-svn: 358702
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 14 |
2 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 09091d3930e..308105fee89 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -1166,6 +1166,8 @@ bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) { MachineInstrBuilder MIB = MIRBuilder.buildIntrinsic(ID, ResultRegs, !CI.doesNotAccessMemory()); + if (isa<FPMathOperator>(CI)) + MIB->copyIRFlags(CI); for (auto &Arg : CI.arg_operands()) { // Some intrinsics take metadata parameters. Reject them. diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index f841492f3a6..f983b02e417 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -1437,10 +1437,11 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) { ConstantFP &ZeroForNegation = *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy)); auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation); - MIRBuilder.buildInstr(TargetOpcode::G_FSUB) - .addDef(Res) - .addUse(Zero->getOperand(0).getReg()) - .addUse(MI.getOperand(1).getReg()); + unsigned SubByReg = MI.getOperand(1).getReg(); + unsigned ZeroReg = Zero->getOperand(0).getReg(); + MachineInstr *SrcMI = MRI.getVRegDef(SubByReg); + MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg}, + SrcMI->getFlags()); MI.eraseFromParent(); return Legalized; } @@ -1455,10 +1456,7 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) { unsigned RHS = MI.getOperand(2).getReg(); unsigned Neg = MRI.createGenericVirtualRegister(Ty); MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS); - MIRBuilder.buildInstr(TargetOpcode::G_FADD) - .addDef(Res) - .addUse(LHS) - .addUse(Neg); + MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags()); MI.eraseFromParent(); return Legalized; } |

