summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
diff options
context:
space:
mode:
authorAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2015-04-30 21:03:29 +0000
committerAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2015-04-30 21:03:29 +0000
commitc84b5bdd695f9c0fa704998528a70fdd9c97bb77 (patch)
treeaf4bcafac164f6faccfdcbac5fb04841625bb177 /llvm/lib/CodeGen
parenta001a32c318d6e48cc16e5f64809ef6d73ad0ae8 (diff)
downloadbcm5719-llvm-c84b5bdd695f9c0fa704998528a70fdd9c97bb77.tar.gz
bcm5719-llvm-c84b5bdd695f9c0fa704998528a70fdd9c97bb77.zip
Fix for PR23103. Correctly propagate the 'IsUndef' flag to the register operands of a commuted instruction.
Revision 220239 exposed a latent bug in method 'TargetInstrInfo::commuteInstruction'. When commuting the operands of a machine instruction, method 'commuteInstruction' didn't correctly propagate the 'IsUndef' flag to the register operands of the new (commuted) instruction. Before this patch, the following instruction: %vreg4<def> = VADDSDrr %vreg14, %vreg5<undef>; FR64:%vreg4,%vreg14,%vreg5 was wrongly converted by method 'commuteInstruction' into: %vreg4<def> = VADDSDrr %vreg5, %vreg14<undef>; FR64:%vreg4,%vreg5,%vreg14 The correct instruction should have been: %vreg4<def> = VADDSDrr %vreg5<undef>, %vreg14; FR64:%vreg4,%vreg5,%vreg14 This patch fixes the problem in method 'TargetInstrInfo::commuteInstruction'. When swapping the operands of a machine instruction, we now make sure that 'IsUndef' flags are correctly set. Added test case 'pr23103.ll'. Differential Revision: http://reviews.llvm.org/D9406 llvm-svn: 236258
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/TargetInstrInfo.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 38725b53b37..165df0696ef 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -142,6 +142,8 @@ MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI,
unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
bool Reg1IsKill = MI->getOperand(Idx1).isKill();
bool Reg2IsKill = MI->getOperand(Idx2).isKill();
+ bool Reg1IsUndef = MI->getOperand(Idx1).isUndef();
+ bool Reg2IsUndef = MI->getOperand(Idx2).isUndef();
// If destination is tied to either of the commuted source register, then
// it must be updated.
if (HasDef && Reg0 == Reg1 &&
@@ -172,6 +174,8 @@ MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI,
MI->getOperand(Idx1).setSubReg(SubReg2);
MI->getOperand(Idx2).setIsKill(Reg1IsKill);
MI->getOperand(Idx1).setIsKill(Reg2IsKill);
+ MI->getOperand(Idx2).setIsUndef(Reg1IsUndef);
+ MI->getOperand(Idx1).setIsUndef(Reg2IsUndef);
return MI;
}
OpenPOWER on IntegriCloud