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authorNirav Dave <niravd@google.com>2019-01-24 15:15:32 +0000
committerNirav Dave <niravd@google.com>2019-01-24 15:15:32 +0000
commitbd069f424f51b8ca695417e020da617a01e87872 (patch)
treefff359e81d454764e29cb7675b8705179c6ed483 /llvm/lib/CodeGen
parent7e552761f39b9b2565845f4625915471c00f1a09 (diff)
downloadbcm5719-llvm-bd069f424f51b8ca695417e020da617a01e87872.tar.gz
bcm5719-llvm-bd069f424f51b8ca695417e020da617a01e87872.zip
[SelectionDAGBuilder] Fuse inline asm input operand loops passes. NFCI.
llvm-svn: 352053
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp22
1 files changed, 9 insertions, 13 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 8c17162c86d..f22ca4b55c3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -7605,19 +7605,6 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
}
- // Third pass - Loop over all of the operands, assigning virtual or physregs
- // to register class operands.
- for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
- SDISelAsmOperandInfo &RefOpInfo =
- OpInfo.isMatchingInputConstraint()
- ? ConstraintOperands[OpInfo.getMatchedOperand()]
- : OpInfo;
-
- if (RefOpInfo.ConstraintType == TargetLowering::C_Register ||
- RefOpInfo.ConstraintType == TargetLowering::C_RegisterClass)
- GetRegistersForValue(DAG, getCurSDLoc(), OpInfo, RefOpInfo);
- }
-
// AsmNodeOperands - The operands for the ISD::INLINEASM node.
std::vector<SDValue> AsmNodeOperands;
AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
@@ -7635,7 +7622,16 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
AsmNodeOperands.push_back(DAG.getTargetConstant(
ExtraInfo.get(), getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
+ // Third pass: Loop over operands to prepare DAG-level operands.. As part of
+ // this, assign virtual and physical registers for inputs and otput.
for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
+ // Assign Registers.
+ SDISelAsmOperandInfo &RefOpInfo =
+ OpInfo.isMatchingInputConstraint()
+ ? ConstraintOperands[OpInfo.getMatchedOperand()]
+ : OpInfo;
+ GetRegistersForValue(DAG, getCurSDLoc(), OpInfo, RefOpInfo);
+
switch (OpInfo.Type) {
case InlineAsm::isOutput:
if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
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