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author | Tom Stellard <thomas.stellard@amd.com> | 2014-06-10 16:01:25 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2014-06-10 16:01:25 +0000 |
commit | b9a023383e9dd4ff82e9862c92450d4d1d193464 (patch) | |
tree | 6667d8b62c67857db3ee2f8d37560a49977b7541 /llvm/lib/CodeGen | |
parent | 3ca1bfc728b5215ae39054f2db20bfb7f51e9413 (diff) | |
download | bcm5719-llvm-b9a023383e9dd4ff82e9862c92450d4d1d193464.tar.gz bcm5719-llvm-b9a023383e9dd4ff82e9862c92450d4d1d193464.zip |
SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors
This prevents a future commit from regressing:
test/CodeGen/R600/setcc-equivalent.ll
llvm-svn: 210540
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index b9da13af752..f1d03f752ac 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2758,24 +2758,24 @@ SDValue DAGCombiner::visitAND(SDNode *N) { ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); - if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && + if (LR == RR && Op0 == Op1 && LL.getValueType().isInteger()) { // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) - if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { + if (TLI.isConstFalseVal(LR.getNode()) && Op1 == ISD::SETEQ) { SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0), LR.getValueType(), LL, RL); AddToWorkList(ORNode.getNode()); return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1); } // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) - if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { + if (TLI.isConstTrueVal(LR.getNode()) && Op1 == ISD::SETEQ) { SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0), LR.getValueType(), LL, RL); AddToWorkList(ANDNode.getNode()); return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1); } // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) - if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { + if (TLI.isConstTrueVal(LR.getNode()) && Op1 == ISD::SETGT) { SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0), LR.getValueType(), LL, RL); AddToWorkList(ORNode.getNode()); |