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authorCraig Topper <craig.topper@intel.com>2018-11-26 21:12:39 +0000
committerCraig Topper <craig.topper@intel.com>2018-11-26 21:12:39 +0000
commitb955bf382cf3ad82c4e8849e898bdfba40ab8aab (patch)
tree4ec62477df784839bd46dd46201c44e205c54848 /llvm/lib/CodeGen
parent5f312ad450d1c91fd626fe6ac68ec731553437ea (diff)
downloadbcm5719-llvm-b955bf382cf3ad82c4e8849e898bdfba40ab8aab.tar.gz
bcm5719-llvm-b955bf382cf3ad82c4e8849e898bdfba40ab8aab.zip
[LegalizeVectorTypes][X86][ARM][AArch64][PowerPC] Don't use SplitVecOp_TruncateHelper for FP_TO_SINT/UINT.
SplitVecOp_TruncateHelper tries to promote the result type while splitting FP_TO_SINT/UINT. It then concatenates the result and introduces a truncate to the original result type. But it does this without inserting the AssertZExt/AssertSExt that the regular result type promotion would insert. Nor does it turn FP_TO_UINT into FP_TO_SINT the way normal result type promotion for these operations does. This is bad on X86 which doesn't support FP_TO_SINT until AVX512. This patch disables the use of SplitVecOp_TruncateHelper for these operations and just lets normal promotion handle it. I've tweaked a couple things in X86ISelLowering to avoid a few obvious regressions there. I believe all the changes on X86 are improvements. The other targets look neutral. Differential Revision: https://reviews.llvm.org/D54906 llvm-svn: 347593
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp9
1 files changed, 2 insertions, 7 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index f34f01cb9fb..2809fcaff4f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -1694,13 +1694,6 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
case ISD::VSELECT:
Res = SplitVecOp_VSELECT(N, OpNo);
break;
- case ISD::FP_TO_SINT:
- case ISD::FP_TO_UINT:
- if (N->getValueType(0).bitsLT(N->getOperand(0).getValueType()))
- Res = SplitVecOp_TruncateHelper(N);
- else
- Res = SplitVecOp_UnaryOp(N);
- break;
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
if (N->getValueType(0).bitsLT(N->getOperand(0).getValueType()))
@@ -1708,6 +1701,8 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
else
Res = SplitVecOp_UnaryOp(N);
break;
+ case ISD::FP_TO_SINT:
+ case ISD::FP_TO_UINT:
case ISD::CTTZ:
case ISD::CTLZ:
case ISD::CTPOP:
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