diff options
| author | Wei Mi <wmi@google.com> | 2016-06-14 18:53:20 +0000 |
|---|---|---|
| committer | Wei Mi <wmi@google.com> | 2016-06-14 18:53:20 +0000 |
| commit | b799a625f9221b017e2ab2503e291c503da6c763 (patch) | |
| tree | 11a43258809590cacd2698956315b61d21259186 /llvm/lib/CodeGen | |
| parent | 07c229c9e7f5520953207ab8cf159674c9bd33f2 (diff) | |
| download | bcm5719-llvm-b799a625f9221b017e2ab2503e291c503da6c763.tar.gz bcm5719-llvm-b799a625f9221b017e2ab2503e291c503da6c763.zip | |
[X86] Reduce the width of multiplification when its operands are extended from i8 or i16
For <N x i32> type mul, pmuludq will be used for targets without SSE41, which
often introduces many extra pack and unpack instructions in vectorized loop
body because pmuludq generates <N/2 x i64> type value. However when the operands
of <N x i32> mul are extended from smaller size values like i8 and i16, the type
of mul may be shrunk to use pmullw + pmulhw/pmulhuw instead of pmuludq, which
generates better code. For targets with SSE41, pmulld is supported so no
shrinking is needed.
Differential Revision: http://reviews.llvm.org/D20931
llvm-svn: 272694
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 9ba68bf2be3..572fecac219 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -670,6 +670,8 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) { case ISD::ADD: case ISD::SUB: case ISD::MUL: + case ISD::MULHS: + case ISD::MULHU: case ISD::FADD: case ISD::FSUB: case ISD::FMUL: |
