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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-08 01:22:47 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-08 01:22:47 +0000 |
commit | adc40baa29a1c16cde63c4bf857afea0eb7b476e (patch) | |
tree | 9e64494325d8fb79a503a06b494779d71c68479b /llvm/lib/CodeGen | |
parent | 8e2bac8e7f77a906a407d73524b2d14304d785dd (diff) | |
download | bcm5719-llvm-adc40baa29a1c16cde63c4bf857afea0eb7b476e.tar.gz bcm5719-llvm-adc40baa29a1c16cde63c4bf857afea0eb7b476e.zip |
RegBankSelect: Fix copy insertion point for terminators
If a copy was needed to handle the condition of brcond, it was being
inserted before the defining instruction. Add tests for iterator edge
cases.
I find the existing code here suspect for the case where it's looking
for terminators that modify the register. It's going to insert a copy
in the middle of the terminators, which isn't allowed (it might be
necessary to have a COPY_terminator if anybody actually needs this).
Also legalize brcond for AMDGPU.
llvm-svn: 350595
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp | 24 |
1 files changed, 15 insertions, 9 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp index 98df7d34857..bfd7a68a8b0 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp @@ -717,15 +717,21 @@ RegBankSelect::RepairingPlacement::RepairingPlacement( unsigned Reg = MO.getReg(); if (Before) { // Check whether Reg is defined by any terminator. - MachineBasicBlock::iterator It = MI; - for (auto Begin = MI.getParent()->begin(); - --It != Begin && It->isTerminator();) - if (It->modifiesRegister(Reg, &TRI)) { - // Insert the repairing code right after the definition. - addInsertPoint(*It, /*Before*/ false); - return; - } - addInsertPoint(*It, /*Before*/ true); + MachineBasicBlock::reverse_iterator It = MI; + auto REnd = MI.getParent()->rend(); + + for (; It != REnd && It->isTerminator(); ++It) { + assert(!It->modifiesRegister(Reg, &TRI) && + "copy insertion in middle of terminators not handled"); + } + + if (It == REnd) { + addInsertPoint(*MI.getParent()->begin(), true); + return; + } + + // We are sure to be right before the first terminator. + addInsertPoint(*It, /*Before*/ false); return; } // Make sure Reg is not redefined by other terminators, otherwise |