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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-06-05 22:58:57 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-06-05 22:58:57 +0000 |
| commit | 9e5b5053d1b9d6ea4a1e2c7e7c59e637ed70b061 (patch) | |
| tree | d2c546e1ba7f01f34f77f144ee3a0f0062ae77fc /llvm/lib/CodeGen | |
| parent | 4d94e994467405321f67339fbb3154e8bbc0b4a0 (diff) | |
| download | bcm5719-llvm-9e5b5053d1b9d6ea4a1e2c7e7c59e637ed70b061.tar.gz bcm5719-llvm-9e5b5053d1b9d6ea4a1e2c7e7c59e637ed70b061.zip | |
RenameIndependentSubregs: Fix handling of undef tied operands
If a tied source operand was undef, it would be replaced but not
update the other tied operand, which would end up using different
virtual registers.
llvm-svn: 304747
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/RenameIndependentSubregs.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp index cc32e43968b..6923716e10c 100644 --- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp +++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp @@ -243,6 +243,11 @@ void RenameIndependentSubregs::rewriteOperands(const IntEqClasses &Classes, unsigned VReg = Intervals[ID]->reg; MO.setReg(VReg); + if (MO.isTied()) { + /// Undef use operands are not tracked in the equivalence class but need + /// to be update if they are tied. + MO.getParent()->substituteRegister(Reg, VReg, 0, TRI); + } } // TODO: We could attempt to recompute new register classes while visiting // the operands: Some of the split register may be fine with less constraint |
