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authorOwen Anderson <resistor@mac.com>2008-08-28 17:47:37 +0000
committerOwen Anderson <resistor@mac.com>2008-08-28 17:47:37 +0000
commit9cd1a5e53067f65b7aafaed1cbdfe89ce73c4aa3 (patch)
tree5cca84f1ee104538766fb98fe2456a79f5cdada3 /llvm/lib/CodeGen
parent04cf2e4540e37fb99f4cb65111e07075c1bac8b7 (diff)
downloadbcm5719-llvm-9cd1a5e53067f65b7aafaed1cbdfe89ce73c4aa3.tar.gz
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FastEmitInst_extractsubreg doesn't need to be passed the register class. It can get it from MachineRegisterInfo instead.
llvm-svn: 55476
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/FastISel.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index 2dd228249b3..4dbfadcd160 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -587,8 +587,8 @@ unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
return ResultReg;
}
-unsigned FastISel::FastEmitInst_extractsubreg(const TargetRegisterClass *RC,
- unsigned Op0, uint32_t Idx) {
+unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) {
+ const TargetRegisterClass* RC = MRI.getRegClass(Op0);
const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
unsigned ResultReg = createResultReg(SRC);
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