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author | Sanjay Patel <spatel@rotateright.com> | 2019-01-10 16:47:42 +0000 |
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committer | Sanjay Patel <spatel@rotateright.com> | 2019-01-10 16:47:42 +0000 |
commit | 9b368f39a987cdf2cd084db76bf44e56a9807451 (patch) | |
tree | e2ce87850f7bf7f624c87d4670c58d38c0d620a7 /llvm/lib/CodeGen | |
parent | ca22fa33911b80d0624f2595efb85bba5bae3e33 (diff) | |
download | bcm5719-llvm-9b368f39a987cdf2cd084db76bf44e56a9807451.tar.gz bcm5719-llvm-9b368f39a987cdf2cd084db76bf44e56a9807451.zip |
[DAGCombiner] simplify code; NFC
llvm-svn: 350844
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 3d5c30ef892..75f8652ff17 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -16913,9 +16913,9 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { // Vi if possible // Only operand 0 is checked as 'concat' assumes all inputs of the same // type. - if (V->getOpcode() == ISD::CONCAT_VECTORS && + if (V.getOpcode() == ISD::CONCAT_VECTORS && isa<ConstantSDNode>(N->getOperand(1)) && - V->getOperand(0).getValueType() == NVT) { + V.getOperand(0).getValueType() == NVT) { unsigned Idx = N->getConstantOperandVal(1); unsigned NumElems = NVT.getVectorNumElements(); assert((Idx % NumElems) == 0 && @@ -16926,9 +16926,9 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { V = peekThroughBitcasts(V); // If the input is a build vector. Try to make a smaller build vector. - if (V->getOpcode() == ISD::BUILD_VECTOR) { + if (V.getOpcode() == ISD::BUILD_VECTOR) { if (auto *Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))) { - EVT InVT = V->getValueType(0); + EVT InVT = V.getValueType(); unsigned ExtractSize = NVT.getSizeInBits(); unsigned EltSize = InVT.getScalarSizeInBits(); // Only do this if we won't split any elements. @@ -16961,16 +16961,16 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { } } - if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { + if (V.getOpcode() == ISD::INSERT_SUBVECTOR) { // Handle only simple case where vector being inserted and vector // being extracted are of same size. - EVT SmallVT = V->getOperand(1).getValueType(); + EVT SmallVT = V.getOperand(1).getValueType(); if (!NVT.bitsEq(SmallVT)) return SDValue(); // Only handle cases where both indexes are constants. - ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); - ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); + auto *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); + auto *InsIdx = dyn_cast<ConstantSDNode>(V.getOperand(2)); if (InsIdx && ExtIdx) { // Combine: @@ -16980,11 +16980,11 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { // otherwise => (extract_subvec V1, ExtIdx) if (InsIdx->getZExtValue() * SmallVT.getScalarSizeInBits() == ExtIdx->getZExtValue() * NVT.getScalarSizeInBits()) - return DAG.getBitcast(NVT, V->getOperand(1)); + return DAG.getBitcast(NVT, V.getOperand(1)); return DAG.getNode( ISD::EXTRACT_SUBVECTOR, SDLoc(N), NVT, - DAG.getBitcast(N->getOperand(0).getValueType(), V->getOperand(0)), - N->getOperand(1)); + DAG.getBitcast(N->getOperand(0).getValueType(), V.getOperand(0)), + N->getOperand(1)); } } |