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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-05-31 18:50:25 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-05-31 18:50:25 +0000 |
| commit | 96ef87e9105ad1cecd72981eaf970982f66b3725 (patch) | |
| tree | e280e019945e7f97e20d33c11cfe2dfc47af4ccf /llvm/lib/CodeGen | |
| parent | e4b3812ec22f8b22108c4705662178e1e081bd73 (diff) | |
| download | bcm5719-llvm-96ef87e9105ad1cecd72981eaf970982f66b3725.tar.gz bcm5719-llvm-96ef87e9105ad1cecd72981eaf970982f66b3725.zip | |
[CodeGen] Promote FMINNAN/FMAXNAN like other binops.
We think it's OK to generate half fminnan because it's legal for the
transform-to type (f32; r245196). However, PromoteFloatRes was missing
the case; simply promote like the other binops, including minnum.
llvm-svn: 271317
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index 38639a2a3a2..a72e55643bc 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -1868,6 +1868,8 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) { // Binary FP Operations case ISD::FADD: case ISD::FDIV: + case ISD::FMAXNAN: + case ISD::FMINNAN: case ISD::FMAXNUM: case ISD::FMINNUM: case ISD::FMUL: |
