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authorCraig Topper <craig.topper@intel.com>2017-11-27 05:52:52 +0000
committerCraig Topper <craig.topper@intel.com>2017-11-27 05:52:52 +0000
commit968491b4e75fb9b1beb12b02873ce954f6b7f7c2 (patch)
tree0d1bbc304f8a02d9b688db3ecbb14bb40adba323 /llvm/lib/CodeGen
parent40007586fcde4f77a4f09fc6b916fba45bb55d84 (diff)
downloadbcm5719-llvm-968491b4e75fb9b1beb12b02873ce954f6b7f7c2.tar.gz
bcm5719-llvm-968491b4e75fb9b1beb12b02873ce954f6b7f7c2.zip
[SelectionDAG] Fix function name in comment. NFC
llvm-svn: 319009
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index a388e0d2618..f15a310bb95 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -243,7 +243,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
// For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
// are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
// legal and was not scalarized.
- // See the similar logic in ScalarizeVecRes_VSETCC
+ // See the similar logic in ScalarizeVecRes_SETCC
if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
Op = GetScalarizedVector(Op);
} else {
@@ -307,7 +307,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
SDLoc DL(N);
// The vselect result and true/value operands needs scalarizing, but it's
// not a given that the Cond does. For instance, in AVX512 v1i1 is legal.
- // See the similar logic in ScalarizeVecRes_VSETCC
+ // See the similar logic in ScalarizeVecRes_SETCC
if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
Cond = GetScalarizedVector(Cond);
} else {
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