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author | Matthias Braun <matze@braunis.de> | 2015-07-14 17:38:17 +0000 |
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committer | Matthias Braun <matze@braunis.de> | 2015-07-14 17:38:17 +0000 |
commit | 953393a72cc0819146d8ada5dc1b84653ecbc73b (patch) | |
tree | a8be3757caa6f79d690f7862d70e676f88379147 /llvm/lib/CodeGen | |
parent | 4ba525b727a416ad688d0237f9f7e6fd697a3c1f (diff) | |
download | bcm5719-llvm-953393a72cc0819146d8ada5dc1b84653ecbc73b.tar.gz bcm5719-llvm-953393a72cc0819146d8ada5dc1b84653ecbc73b.zip |
RAGreedy: Keep track of allocated PhysRegs internally
Do not use MachineRegisterInfo::setPhysRegUsed()/isPhysRegUsed()
anymore. This bitset changes function-global state and is set by the
VirtRegRewriter anyway.
Simply use a bitvector private to RAGreedy.
Differential Revision: http://reviews.llvm.org/D10910
llvm-svn: 242169
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r-- | llvm/lib/CodeGen/LiveRegMatrix.cpp | 8 | ||||
-rw-r--r-- | llvm/lib/CodeGen/RegAllocGreedy.cpp | 42 |
2 files changed, 32 insertions, 18 deletions
diff --git a/llvm/lib/CodeGen/LiveRegMatrix.cpp b/llvm/lib/CodeGen/LiveRegMatrix.cpp index 154ce6fc122..9ea031d38d2 100644 --- a/llvm/lib/CodeGen/LiveRegMatrix.cpp +++ b/llvm/lib/CodeGen/LiveRegMatrix.cpp @@ -131,6 +131,14 @@ void LiveRegMatrix::unassign(LiveInterval &VirtReg) { DEBUG(dbgs() << '\n'); } +bool LiveRegMatrix::isPhysRegUsed(unsigned PhysReg) const { + for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) { + if (!Matrix[*Unit].empty()) + return true; + } + return false; +} + bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg) { // Check if the cached information is valid. diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp index 26f42c93323..7ebcf7f5485 100644 --- a/llvm/lib/CodeGen/RegAllocGreedy.cpp +++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp @@ -400,6 +400,8 @@ private: typedef SmallVector<HintInfo, 4> HintsInfo; BlockFrequency getBrokenHintFreq(const HintsInfo &, unsigned); void collectHintInfo(unsigned, HintsInfo &); + + bool isUnusedCalleeSavedReg(unsigned PhysReg) const; }; } // end anonymous namespace @@ -816,6 +818,16 @@ void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, } } +/// Returns true if the given \p PhysReg is a callee saved register and has not +/// been used for allocation yet. +bool RAGreedy::isUnusedCalleeSavedReg(unsigned PhysReg) const { + unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg); + if (CSR == 0) + return false; + + return !Matrix->isPhysRegUsed(PhysReg); +} + /// tryEvict - Try to evict all interferences for a physreg. /// @param VirtReg Currently unassigned virtual register. /// @param Order Physregs to try. @@ -861,13 +873,12 @@ unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, continue; // The first use of a callee-saved register in a function has cost 1. // Don't start using a CSR when the CostPerUseLimit is low. - if (CostPerUseLimit == 1) - if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg)) - if (!MRI->isPhysRegUsed(CSR)) { - DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR " - << PrintReg(CSR, TRI) << '\n'); - continue; - } + if (CostPerUseLimit == 1 && isUnusedCalleeSavedReg(PhysReg)) { + DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " would clobber CSR " + << PrintReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) + << '\n'); + continue; + } if (!canEvictInterference(VirtReg, PhysReg, false, BestCost)) continue; @@ -1348,9 +1359,8 @@ unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg, unsigned BestCand = NoCand; Order.rewind(); while (unsigned PhysReg = Order.next()) { - if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg)) - if (IgnoreCSR && !MRI->isPhysRegUsed(CSR)) - continue; + if (IgnoreCSR && isUnusedCalleeSavedReg(PhysReg)) + continue; // Discard bad candidates before we run out of interference cache cursors. // This will only affect register classes with a lot of registers (>32). @@ -2134,7 +2144,8 @@ unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg, unsigned ItVirtReg = (*It)->reg; if (VRM->hasPhys(ItVirtReg)) Matrix->unassign(**It); - Matrix->assign(**It, VirtRegToPhysReg[ItVirtReg]); + unsigned ItPhysReg = VirtRegToPhysReg[ItVirtReg]; + Matrix->assign(**It, ItPhysReg); } } @@ -2441,16 +2452,11 @@ unsigned RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg, // First try assigning a free register. AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo); if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) { - // We check other options if we are using a CSR for the first time. - bool CSRFirstUse = false; - if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg)) - if (!MRI->isPhysRegUsed(CSR)) - CSRFirstUse = true; - // When NewVRegs is not empty, we may have made decisions such as evicting // a virtual register, go with the earlier decisions and use the physical // register. - if (CSRCost.getFrequency() && CSRFirstUse && NewVRegs.empty()) { + if (CSRCost.getFrequency() && isUnusedCalleeSavedReg(PhysReg) && + NewVRegs.empty()) { unsigned CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg, CostPerUseLimit, NewVRegs); if (CSRReg || !NewVRegs.empty()) |