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authorCraig Topper <craig.topper@intel.com>2017-09-11 16:15:39 +0000
committerCraig Topper <craig.topper@intel.com>2017-09-11 16:15:39 +0000
commit8dff57a0ed76774a2a743bdd73b6f48aeff08212 (patch)
treeb84d0f9198ab1ef2f3f0412f16eb404f50dda620 /llvm/lib/CodeGen
parentbc455478e10907c28270b4eb241d26c79595cfe8 (diff)
downloadbcm5719-llvm-8dff57a0ed76774a2a743bdd73b6f48aeff08212.tar.gz
bcm5719-llvm-8dff57a0ed76774a2a743bdd73b6f48aeff08212.zip
[SelectionDAG] Remove a check for type being a vector type after calling getShiftAmountTy. NFCI
getShiftAmountTy already returns the vector type when called for vectors. llvm-svn: 312924
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp2
1 files changed, 0 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 3a55e4da1ab..ba944f60f7b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2985,8 +2985,6 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
// NOTE: we could fall back on load/store here too for targets without
// SRA. However, it is doubtful that any exist.
EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
- if (VT.isVector())
- ShiftAmountTy = VT;
unsigned BitsDiff = VT.getScalarSizeInBits() -
ExtraVT.getScalarSizeInBits();
SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
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