Reject really weird coalescer case when trying to merge identical subregisters

of different register classes. e.g.

  %reg1048:3<def> = EXTRACT_SUBREG %RAX<kill>, 3

Where %reg1048 is a GR32 register. This is not impossible to handle, but it is
pretty hard and very rare.

This should unbreak the dragonegg builder.

llvm-svn: 102672

1 files changed, 7 insertions, 0 deletions

diff --git a/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp b/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
index e7c758db092..da96f232b80 100644
--- a/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -1394,6 +1394,13 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
     return false;  // Not coalescable.
   }
 
+  // We cannot handle dual subreg indices and mismatched classes at the same
+  // time.
+  if (SrcSubIdx && DstSubIdx && differingRegisterClasses(SrcReg, DstReg)) {
+    DEBUG(dbgs() << "\tCannot handle subreg indices and mismatched classes.\n");
+    return false;
+  }
+
   // Check that a physical source register is compatible with dst regclass
   if (SrcIsPhys) {
     unsigned SrcSubReg = SrcSubIdx ?