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author | Alexey Samsonov <vonosmas@gmail.com> | 2014-08-20 19:36:05 +0000 |
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committer | Alexey Samsonov <vonosmas@gmail.com> | 2014-08-20 19:36:05 +0000 |
commit | 8968e6d1b02543d12e312f1be6edd152b89de584 (patch) | |
tree | e0a9f8a8404b21f5f96a52db2fd9c2ac71349303 /llvm/lib/CodeGen | |
parent | d750723d291dc6cd9295b7b0643b71d8cd9fbab2 (diff) | |
download | bcm5719-llvm-8968e6d1b02543d12e312f1be6edd152b89de584.tar.gz bcm5719-llvm-8968e6d1b02543d12e312f1be6edd152b89de584.zip |
Fix null reference creation in ScheduleDAGInstrs constructor call.
Both MachineLoopInfo and MachineDominatorTree may be null in ScheduleDAGMI
constructor call. It is undefined behavior to take references to these values.
This bug is reported by UBSan.
llvm-svn: 216118
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r-- | llvm/lib/CodeGen/DFAPacketizer.cpp | 2 | ||||
-rw-r--r-- | llvm/lib/CodeGen/PostRASchedulerList.cpp | 2 | ||||
-rw-r--r-- | llvm/lib/CodeGen/ScheduleDAGInstrs.cpp | 4 |
3 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/DFAPacketizer.cpp b/llvm/lib/CodeGen/DFAPacketizer.cpp index cce4c484c9b..67a2664d56a 100644 --- a/llvm/lib/CodeGen/DFAPacketizer.cpp +++ b/llvm/lib/CodeGen/DFAPacketizer.cpp @@ -115,7 +115,7 @@ public: DefaultVLIWScheduler::DefaultVLIWScheduler( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, bool IsPostRA) : - ScheduleDAGInstrs(MF, MLI, MDT, IsPostRA) { + ScheduleDAGInstrs(MF, &MLI, &MDT, IsPostRA) { CanHandleTerminators = true; } diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index a1f3e5b07ea..5a87fd938ea 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -197,7 +197,7 @@ SchedulePostRATDList::SchedulePostRATDList( AliasAnalysis *AA, const RegisterClassInfo &RCI, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs) - : ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), AA(AA), EndIndex(0) { + : ScheduleDAGInstrs(MF, &MLI, &MDT, /*IsPostRA=*/true), AA(AA), EndIndex(0) { const TargetMachine &TM = MF.getTarget(); const InstrItineraryData *InstrItins = diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp index 213889dc5c4..e1278d05597 100644 --- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -50,8 +50,8 @@ static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, cl::init(true), cl::desc("Enable use of TBAA during MI GAD construction")); ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, - const MachineLoopInfo &mli, - const MachineDominatorTree &mdt, + const MachineLoopInfo *mli, + const MachineDominatorTree *mdt, bool IsPostRAFlag, bool RemoveKillFlags, LiveIntervals *lis) |