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authorSanjay Patel <spatel@rotateright.com>2016-10-11 16:26:36 +0000
committerSanjay Patel <spatel@rotateright.com>2016-10-11 16:26:36 +0000
commit8384703d9bf093a3d1ead01ffb7e5b93285c515b (patch)
tree6fa89cf665b22c0935627afa0c085c2310c7dc30 /llvm/lib/CodeGen
parentb617286089cac5a3f2a71c9aa60ed9f16621e698 (diff)
downloadbcm5719-llvm-8384703d9bf093a3d1ead01ffb7e5b93285c515b.tar.gz
bcm5719-llvm-8384703d9bf093a3d1ead01ffb7e5b93285c515b.zip
[DAG] add fold for masked negated extended bool
The non-obvious motivation for adding this fold (which already happens in InstCombine) is that we want to canonicalize IR towards select instructions and canonicalize DAG nodes towards boolean math. So we need to recreate some folds in the DAG to handle that change in direction. An interesting implementation difference for cases like this is that InstCombine generally works top-down while the DAG goes bottom-up. That means we need to detect different patterns. In this case, the SimplifyDemandedBits fold prevents us from performing a zext to sext fold that would then be recognized as a negation of a sext. llvm-svn: 283900
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp17
1 files changed, 15 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index a00a48c9b5d..7118b4cbf0e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3314,10 +3314,23 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
if (SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N))
return Tmp;
+ // Masking the negated extension of a boolean is just the extended boolean:
+ // and (sub 0, zext(bool X)), 1 --> zext(bool X)
+ //
+ // Note: the SimplifyDemandedBits fold below can make an information-losing
+ // transform, and then we have no way to find this better fold.
+ if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) {
+ ConstantSDNode *SubLHS = isConstOrConstSplat(N0.getOperand(0));
+ SDValue SubRHS = N0.getOperand(1);
+ if (SubLHS && SubLHS->isNullValue() &&
+ SubRHS.getOpcode() == ISD::ZERO_EXTEND &&
+ SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
+ return SubRHS;
+ }
+
// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
// fold (and (sra)) -> (and (srl)) when possible.
- if (!VT.isVector() &&
- SimplifyDemandedBits(SDValue(N, 0)))
+ if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
return SDValue(N, 0);
// fold (zext_inreg (extload x)) -> (zextload x)
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