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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-06-27 18:28:10 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2017-06-27 18:28:10 +0000 |
| commit | 836d786e860b989a065d74732d54309ab94bad2a (patch) | |
| tree | 190c329010d04b6c41e2ec3124eb707085ab2d26 /llvm/lib/CodeGen | |
| parent | 7c44f340de6b879959a54dd0d2ba85af6282cc48 (diff) | |
| download | bcm5719-llvm-836d786e860b989a065d74732d54309ab94bad2a.tar.gz bcm5719-llvm-836d786e860b989a065d74732d54309ab94bad2a.zip | |
RenameIndependentSubregs: Fix infinite loop
Apparently this replacement can really be substituting the
same as the original register. Avoid restarting the loop
when there's been no change in the register uses.
llvm-svn: 306441
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/RenameIndependentSubregs.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp index a5abd500080..bd5ecbd28f2 100644 --- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp +++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp @@ -243,7 +243,8 @@ void RenameIndependentSubregs::rewriteOperands(const IntEqClasses &Classes, unsigned VReg = Intervals[ID]->reg; MO.setReg(VReg); - if (MO.isTied()) { + + if (MO.isTied() && Reg != VReg) { /// Undef use operands are not tracked in the equivalence class but need /// to be update if they are tied. MO.getParent()->substituteRegister(Reg, VReg, 0, TRI); |
