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authorZachary Turner <zturner@google.com>2017-12-01 00:53:10 +0000
committerZachary Turner <zturner@google.com>2017-12-01 00:53:10 +0000
commit8065f0b975022c1419ab6c1ee6dca64b209311dc (patch)
tree014b235430c601a19300b725575ac65e37d44e3e /llvm/lib/CodeGen
parent888a42829238a00fd7e5d6daf07d48324699f5f2 (diff)
downloadbcm5719-llvm-8065f0b975022c1419ab6c1ee6dca64b209311dc.tar.gz
bcm5719-llvm-8065f0b975022c1419ab6c1ee6dca64b209311dc.zip
Mark all library options as hidden.
These command line options are not intended for public use, and often don't even make sense in the context of a particular tool anyway. About 90% of them are already hidden, but when people add new options they forget to hide them, so if you were to make a brand new tool today, link against one of LLVM's libraries, and run tool -help you would get a bunch of junk that doesn't make sense for the tool you're writing. This patch hides these options. The real solution is to not have libraries defining command line options, but that's a much larger effort and not something I'm prepared to take on. Differential Revision: https://reviews.llvm.org/D40674 llvm-svn: 319505
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/ImplicitNullChecks.cpp4
-rw-r--r--llvm/lib/CodeGen/MIRPrinter.cpp3
-rw-r--r--llvm/lib/CodeGen/MachineDominators.cpp2
-rw-r--r--llvm/lib/CodeGen/RegAllocBase.cpp4
-rw-r--r--llvm/lib/CodeGen/RegAllocGreedy.cpp9
-rw-r--r--llvm/lib/CodeGen/RegisterCoalescer.cpp7
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp10
-rw-r--r--llvm/lib/CodeGen/StackMaps.cpp2
-rw-r--r--llvm/lib/CodeGen/TargetPassConfig.cpp32
9 files changed, 36 insertions, 37 deletions
diff --git a/llvm/lib/CodeGen/ImplicitNullChecks.cpp b/llvm/lib/CodeGen/ImplicitNullChecks.cpp
index 02c7eeb7a48..1962b4ca65d 100644
--- a/llvm/lib/CodeGen/ImplicitNullChecks.cpp
+++ b/llvm/lib/CodeGen/ImplicitNullChecks.cpp
@@ -63,13 +63,13 @@ using namespace llvm;
static cl::opt<int> PageSize("imp-null-check-page-size",
cl::desc("The page size of the target in bytes"),
- cl::init(4096));
+ cl::init(4096), cl::Hidden);
static cl::opt<unsigned> MaxInstsToConsider(
"imp-null-max-insts-to-consider",
cl::desc("The max number of instructions to consider hoisting loads over "
"(the algorithm is quadratic over this number)"),
- cl::init(8));
+ cl::Hidden, cl::init(8));
#define DEBUG_TYPE "implicit-null-checks"
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index e437a528115..92dc0aea421 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -75,7 +75,8 @@
using namespace llvm;
-static cl::opt<bool> SimplifyMIR("simplify-mir",
+static cl::opt<bool> SimplifyMIR(
+ "simplify-mir", cl::Hidden,
cl::desc("Leave out unnecessary information when printing MIR"));
namespace {
diff --git a/llvm/lib/CodeGen/MachineDominators.cpp b/llvm/lib/CodeGen/MachineDominators.cpp
index 845e8232477..fcfa574ee6c 100644
--- a/llvm/lib/CodeGen/MachineDominators.cpp
+++ b/llvm/lib/CodeGen/MachineDominators.cpp
@@ -26,7 +26,7 @@ static bool VerifyMachineDomInfo = true;
static bool VerifyMachineDomInfo = false;
#endif
static cl::opt<bool, true> VerifyMachineDomInfoX(
- "verify-machine-dom-info", cl::location(VerifyMachineDomInfo),
+ "verify-machine-dom-info", cl::location(VerifyMachineDomInfo), cl::Hidden,
cl::desc("Verify machine dominator info (time consuming)"));
namespace llvm {
diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp b/llvm/lib/CodeGen/RegAllocBase.cpp
index 6b67fd85667..f41a3ad000d 100644
--- a/llvm/lib/CodeGen/RegAllocBase.cpp
+++ b/llvm/lib/CodeGen/RegAllocBase.cpp
@@ -40,8 +40,8 @@ STATISTIC(NumNewQueued , "Number of new live ranges queued");
// Temporary verification option until we can put verification inside
// MachineVerifier.
static cl::opt<bool, true>
-VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
- cl::desc("Verify during register allocation"));
+ VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
+ cl::Hidden, cl::desc("Verify during register allocation"));
const char RegAllocBase::TimerGroupName[] = "regalloc";
const char RegAllocBase::TimerGroupDescription[] = "Register Allocation";
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index c3d94d8a5eb..131cd5a17ef 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -105,10 +105,11 @@ static cl::opt<unsigned> LastChanceRecoloringMaxInterference(
" interference at a time"),
cl::init(8));
-static cl::opt<bool>
-ExhaustiveSearch("exhaustive-register-search", cl::NotHidden,
- cl::desc("Exhaustive Search for registers bypassing the depth "
- "and interference cutoffs of last chance recoloring"));
+static cl::opt<bool> ExhaustiveSearch(
+ "exhaustive-register-search", cl::NotHidden,
+ cl::desc("Exhaustive Search for registers bypassing the depth "
+ "and interference cutoffs of last chance recoloring"),
+ cl::Hidden);
static cl::opt<bool> EnableLocalReassignment(
"enable-local-reassign", cl::Hidden,
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 128a07cef10..2bbefa97132 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -70,10 +70,9 @@ STATISTIC(NumInflated , "Number of register classes inflated");
STATISTIC(NumLaneConflicts, "Number of dead lane conflicts tested");
STATISTIC(NumLaneResolves, "Number of dead lane conflicts resolved");
-static cl::opt<bool>
-EnableJoining("join-liveintervals",
- cl::desc("Coalesce copies (default=true)"),
- cl::init(true));
+static cl::opt<bool> EnableJoining("join-liveintervals",
+ cl::desc("Coalesce copies (default=true)"),
+ cl::init(true), cl::Hidden);
static cl::opt<bool> UseTerminalRule("terminal-rule",
cl::desc("Apply the terminal rule"),
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 3d850d05873..498aa94eb83 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -128,11 +128,11 @@ using namespace llvm;
static unsigned LimitFloatPrecision;
static cl::opt<unsigned, true>
-LimitFPPrecision("limit-float-precision",
- cl::desc("Generate low-precision inline sequences "
- "for some float libcalls"),
- cl::location(LimitFloatPrecision),
- cl::init(0));
+ LimitFPPrecision("limit-float-precision",
+ cl::desc("Generate low-precision inline sequences "
+ "for some float libcalls"),
+ cl::location(LimitFloatPrecision), cl::Hidden,
+ cl::init(0));
static cl::opt<unsigned> SwitchPeelThreshold(
"switch-peel-threshold", cl::Hidden, cl::init(66),
diff --git a/llvm/lib/CodeGen/StackMaps.cpp b/llvm/lib/CodeGen/StackMaps.cpp
index 8d502bdae38..e66a25bec91 100644
--- a/llvm/lib/CodeGen/StackMaps.cpp
+++ b/llvm/lib/CodeGen/StackMaps.cpp
@@ -41,7 +41,7 @@ using namespace llvm;
#define DEBUG_TYPE "stackmaps"
static cl::opt<int> StackMapVersion(
- "stackmap-version", cl::init(3),
+ "stackmap-version", cl::init(3), cl::Hidden,
cl::desc("Specify the stackmap encoding version (default = 3)"));
const char *StackMaps::WSMP = "Stack Maps: ";
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index 3f2a31a69cf..121bed5a79c 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -93,11 +93,11 @@ static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inli
static cl::opt<bool> EnableImplicitNullChecks(
"enable-implicit-null-checks",
cl::desc("Fold null checks into faulting memory operations"),
- cl::init(false));
-static cl::opt<bool> EnableMergeICmps(
- "enable-mergeicmps",
- cl::desc("Merge ICmp chains into a single memcmp"),
- cl::init(false));
+ cl::init(false), cl::Hidden);
+static cl::opt<bool>
+ EnableMergeICmps("enable-mergeicmps",
+ cl::desc("Merge ICmp chains into a single memcmp"),
+ cl::init(false), cl::Hidden);
static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
cl::desc("Print LLVM IR produced by the loop-reduce pass"));
static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
@@ -127,10 +127,9 @@ static cl::opt<cl::boolOrDefault>
EnableGlobalISel("global-isel", cl::Hidden,
cl::desc("Enable the \"global\" instruction selector"));
-static cl::opt<std::string>
-PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
- cl::desc("Print machine instrs"),
- cl::value_desc("pass-name"), cl::init("option-unspecified"));
+static cl::opt<std::string> PrintMachineInstrs(
+ "print-machineinstrs", cl::ValueOptional, cl::desc("Print machine instrs"),
+ cl::value_desc("pass-name"), cl::init("option-unspecified"), cl::Hidden);
static cl::opt<int> EnableGlobalISelAbort(
"global-isel-abort", cl::Hidden,
@@ -176,22 +175,22 @@ const char *StopBeforeOptName = "stop-before";
static cl::opt<std::string>
StartAfterOpt(StringRef(StartAfterOptName),
cl::desc("Resume compilation after a specific pass"),
- cl::value_desc("pass-name"), cl::init(""));
+ cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
static cl::opt<std::string>
StartBeforeOpt(StringRef(StartBeforeOptName),
cl::desc("Resume compilation before a specific pass"),
- cl::value_desc("pass-name"), cl::init(""));
+ cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
static cl::opt<std::string>
StopAfterOpt(StringRef(StopAfterOptName),
cl::desc("Stop compilation after a specific pass"),
- cl::value_desc("pass-name"), cl::init(""));
+ cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
static cl::opt<std::string>
StopBeforeOpt(StringRef(StopBeforeOptName),
cl::desc("Stop compilation before a specific pass"),
- cl::value_desc("pass-name"), cl::init(""));
+ cl::value_desc("pass-name"), cl::init(""), cl::Hidden);
/// Allow standard passes to be disabled by command line options. This supports
/// simple binary flags that either suppress the pass or do nothing.
@@ -767,10 +766,9 @@ bool TargetPassConfig::addISelPasses() {
/// -regalloc=... command line option.
static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
- RegisterPassParser<RegisterRegAlloc> >
-RegAlloc("regalloc",
- cl::init(&useDefaultRegisterAllocator),
- cl::desc("Register allocator to use"));
+ RegisterPassParser<RegisterRegAlloc>>
+ RegAlloc("regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
+ cl::desc("Register allocator to use"));
/// Add the complete set of target-independent postISel code generator passes.
///
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