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authorSanjay Patel <spatel@rotateright.com>2018-07-15 17:09:35 +0000
committerSanjay Patel <spatel@rotateright.com>2018-07-15 17:09:35 +0000
commit79a423cfa2de75dcf89b270b4ccb0a50b0d40802 (patch)
tree373468e9ee87b523e2f5e8a0eea5a72e5526dfdd /llvm/lib/CodeGen
parent9d2099cc0368e0ce5d8b16876a52b3a5a8360853 (diff)
downloadbcm5719-llvm-79a423cfa2de75dcf89b270b4ccb0a50b0d40802.tar.gz
bcm5719-llvm-79a423cfa2de75dcf89b270b4ccb0a50b0d40802.zip
[DAGCombiner] fix typo in comment; NFC
llvm-svn: 337132
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 2825e45c541..17c483266cc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8115,7 +8115,7 @@ static SDValue foldExtendedSignBitTest(SDNode *N, SelectionDAG &DAG,
EVT VT = N->getValueType(0);
EVT XVT = X.getValueType();
// setge X, C is canonicalized to setgt, so we do not need to match that
- // pattern. The setlt sibling is folded in SimplifySelectCC() becaus it does
+ // pattern. The setlt sibling is folded in SimplifySelectCC() because it does
// not require the 'not' op.
if (CC == ISD::SETGT && isAllOnesConstant(Ones) && VT == XVT) {
// Invert and smear/shift the sign bit:
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