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| author | Clement Courbet <courbet@google.com> | 2018-12-13 09:56:19 +0000 |
|---|---|---|
| committer | Clement Courbet <courbet@google.com> | 2018-12-13 09:56:19 +0000 |
| commit | 76f4ae109266fae1d17cade097a14216bc10822e (patch) | |
| tree | 25d0590be62d8c00aa7c8ed652d23869ad92a3ae /llvm/lib/CodeGen | |
| parent | a257639a6935a2c63377784c5c9c3b73864a2582 (diff) | |
| download | bcm5719-llvm-76f4ae109266fae1d17cade097a14216bc10822e.tar.gz bcm5719-llvm-76f4ae109266fae1d17cade097a14216bc10822e.zip | |
[CodeGen] Allow mempcy/memset to generate small overlapping stores.
Summary:
All targets either just return false here or properly model `Fast`, so I
don't think there is any reason to prevent CodeGen from doing the right
thing here.
Subscribers: nemanjai, javed.absar, eraman, jsji, llvm-commits
Differential Revision: https://reviews.llvm.org/D55365
llvm-svn: 349016
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 62bb94ccba2..ceb86898946 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -5491,12 +5491,10 @@ static bool FindOptimalMemOpLowering(std::vector<EVT> &MemOps, // If the new VT cannot cover all of the remaining bits, then consider // issuing a (or a pair of) unaligned and overlapping load / store. - // FIXME: Only does this for 64-bit or more since we don't have proper - // cost model for unaligned load / store. bool Fast; - if (NumMemOps && AllowOverlap && - VTSize >= 8 && NewVTSize < Size && - TLI.allowsMisalignedMemoryAccesses(VT, DstAS, DstAlign, &Fast) && Fast) + if (NumMemOps && AllowOverlap && NewVTSize < Size && + TLI.allowsMisalignedMemoryAccesses(VT, DstAS, DstAlign, &Fast) && + Fast) VTSize = Size; else { VT = NewVT; |
