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authorOwen Anderson <resistor@mac.com>2008-09-10 20:41:13 +0000
committerOwen Anderson <resistor@mac.com>2008-09-10 20:41:13 +0000
commit7591130946662120b551be0b4d6977d88d9c0efe (patch)
tree4aa8503fc58ca6bf9b48852e15c40c0e772fd534 /llvm/lib/CodeGen
parent39d82f902aa716ddc9b4cc1ac32acf79b3fbe46c (diff)
downloadbcm5719-llvm-7591130946662120b551be0b4d6977d88d9c0efe.tar.gz
bcm5719-llvm-7591130946662120b551be0b4d6977d88d9c0efe.zip
Fix a bug in the coalescer where it didn't check if a live interval existed before trying to manipulate it. This
was exposed by fast isel's handling of shifts on X86-64. With this, FreeBench/pcompress2 passes on X86-64 in fast isel. llvm-svn: 56067
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp b/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
index cca891d7735..c6d4576e9c9 100644
--- a/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -464,7 +464,7 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
MachineOperand &MO = CopyMI->getOperand(i);
if (MO.isReg() && MO.isImplicit())
NewMI->addOperand(MO);
- if (MO.isDef()) {
+ if (MO.isDef() && li_->hasInterval(MO.getReg())) {
unsigned Reg = MO.getReg();
DLR = li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
if (DLR && DLR->valno->copy == CopyMI)
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