[DAG] avoid creating illegal node when transforming negated shifted sign bit

Eli noted this potential bug in the post-commit thread for:
https://reviews.llvm.org/rL284239
...but I'm not sure how to trigger it, so there's no test case yet.

llvm-svn: 284268

1 files changed, 3 insertions, 2 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 031edb615b8..44a49e848aa 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1962,8 +1962,9 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
       (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL)) {
     ConstantSDNode *ShiftAmt = isConstOrConstSplat(N1.getOperand(1));
     if (ShiftAmt && ShiftAmt->getZExtValue() == VT.getScalarSizeInBits() - 1) {
-      auto NewOpcode = N1->getOpcode() == ISD::SRA ? ISD::SRL :ISD::SRA;
-      return DAG.getNode(NewOpcode, DL, VT, N1.getOperand(0), N1.getOperand(1));
+      auto NewOpc = N1->getOpcode() == ISD::SRA ? ISD::SRL :ISD::SRA;
+      if (!LegalOperations || TLI.isOperationLegal(NewOpc, VT))
+        return DAG.getNode(NewOpc, DL, VT, N1.getOperand(0), N1.getOperand(1));
     }
   }