summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
diff options
context:
space:
mode:
authorPete Cooper <peter_cooper@apple.com>2015-05-05 18:31:36 +0000
committerPete Cooper <peter_cooper@apple.com>2015-05-05 18:31:36 +0000
commit6ebc207703607521b4cab5b211332a2a86757538 (patch)
tree0ce94fa2f238b901b96094078f9977fd4f43f38f /llvm/lib/CodeGen
parentbbd1c727d17afb1d8327b8a49eb36a716c9af8c0 (diff)
downloadbcm5719-llvm-6ebc207703607521b4cab5b211332a2a86757538.tar.gz
bcm5719-llvm-6ebc207703607521b4cab5b211332a2a86757538.zip
Fix IfConverter to handle regmask machine operands.
A regmask (typically seen on a call) clobbers the set of registers it lists. The IfConverter, in UpdatePredRedefs, was handling register defs, but not regmasks. These are slightly different to a def in that we need to add both an implicit use and def to appease the machine verifier. Otherwise, uses after the if converted call could think they are reading an undefined register. Reviewed by Matthias Braun and Quentin Colombet. llvm-svn: 236515
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/IfConversion.cpp14
1 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp
index 938c9cf6039..4bad70925d7 100644
--- a/llvm/lib/CodeGen/IfConversion.cpp
+++ b/llvm/lib/CodeGen/IfConversion.cpp
@@ -985,6 +985,20 @@ static void UpdatePredRedefs(MachineInstr *MI, LivePhysRegs &Redefs) {
// take a mutable instruction instead of const.
MachineInstr *OpMI = const_cast<MachineInstr*>(Op.getParent());
MachineInstrBuilder MIB(*OpMI->getParent()->getParent(), OpMI);
+
+ if (Op.isRegMask()) {
+ // First handle regmasks. They clobber any entries in the mask which
+ // means that we need a def for those registers.
+ MIB.addReg(Reg.first, RegState::Implicit | RegState::Undef);
+
+ // We also need to add an implicit def of this register for the later
+ // use to read from.
+ // For the register allocator to have allocated a register clobbered
+ // by the call which is used later, it must be the case that
+ // the call doesn't return.
+ MIB.addReg(Reg.first, RegState::Implicit | RegState::Define);
+ continue;
+ }
assert(Op.isReg() && "Register operand required");
MIB.addReg(Reg.first, RegState::Implicit | RegState::Undef);
}
OpenPOWER on IntegriCloud