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authorMatt Arsenault <Matthew.Arsenault@amd.com>2016-09-07 06:16:45 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2016-09-07 06:16:45 +0000
commit6cda10c9503e7754feed72346c9dee7ef73a72d5 (patch)
tree34f7241f582be8e0545435d1d8af0c9db3ba62eb /llvm/lib/CodeGen
parent0e473955a02768652ec0a50a08528750d724d847 (diff)
downloadbcm5719-llvm-6cda10c9503e7754feed72346c9dee7ef73a72d5.tar.gz
bcm5719-llvm-6cda10c9503e7754feed72346c9dee7ef73a72d5.zip
Remove unnecessary call to getAllocatableRegClass
This reapplies r252565 and r252674, effectively reverting r252956. This allows VS_32/VS_64 to be unallocatable like they should be. llvm-svn: 280783
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp24
1 files changed, 15 insertions, 9 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index c8af73a3b44..d760a70b1f3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -330,16 +330,22 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
// shrink VReg's register class within reason. For example, if VReg == GR32
// and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
if (II) {
- const TargetRegisterClass *DstRC = nullptr;
+ const TargetRegisterClass *OpRC = nullptr;
if (IIOpNum < II->getNumOperands())
- DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
- assert((!DstRC || TargetRegisterInfo::isVirtualRegister(VReg)) &&
- "Expected VReg");
- if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
- unsigned NewVReg = MRI->createVirtualRegister(DstRC);
- BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
- TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
- VReg = NewVReg;
+ OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
+
+ if (OpRC) {
+ const TargetRegisterClass *ConstrainedRC
+ = MRI->constrainRegClass(VReg, OpRC, MinRCSize);
+ if (!ConstrainedRC) {
+ unsigned NewVReg = MRI->createVirtualRegister(OpRC);
+ BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
+ TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
+ VReg = NewVReg;
+ } else {
+ assert(ConstrainedRC->isAllocatable() &&
+ "Constraining an allocatable VReg produced an unallocatable class?");
+ }
}
}
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