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| author | Diana Picus <diana.picus@linaro.org> | 2019-06-27 08:50:53 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2019-06-27 08:50:53 +0000 |
| commit | 69ce1c1319634dbf8bc3d6cb4305efea2da0965f (patch) | |
| tree | 8c69df9e5994613d7bea68f951efe1cb827fd66c /llvm/lib/CodeGen | |
| parent | 8479240b0a62efa0481f60db81a60f7638079003 (diff) | |
| download | bcm5719-llvm-69ce1c1319634dbf8bc3d6cb4305efea2da0965f.tar.gz bcm5719-llvm-69ce1c1319634dbf8bc3d6cb4305efea2da0965f.zip | |
[GlobalISel] Allow multiple VRegs in ArgInfo. NFC
Allow CallLowering::ArgInfo to contain more than one virtual register.
This is useful when passes split aggregates into several virtual
registers, but need to also provide information about the original type
to the call lowering. Used in follow-up patches.
Differential Revision: https://reviews.llvm.org/D63548
llvm-svn: 364509
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 14 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 |
2 files changed, 11 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp index 99143a40c64..e8ffd713ddd 100644 --- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp @@ -150,6 +150,12 @@ bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder, continue; } + assert(Args[i].Regs.size() == 1 && + "Can't handle multiple virtual regs yet"); + + // FIXME: Pack registers if we have more than one. + unsigned ArgReg = Args[i].Regs[0]; + if (VA.isRegLoc()) { MVT OrigVT = MVT::getVT(Args[i].Ty); MVT VAVT = VA.getValVT(); @@ -172,12 +178,12 @@ bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder, return false; } auto Unmerge = MIRBuilder.buildUnmerge({OrigTy, OrigTy}, {NewReg}); - MIRBuilder.buildCopy(Args[i].Reg, Unmerge.getReg(0)); + MIRBuilder.buildCopy(ArgReg, Unmerge.getReg(0)); } else { - MIRBuilder.buildTrunc(Args[i].Reg, {NewReg}).getReg(0); + MIRBuilder.buildTrunc(ArgReg, {NewReg}).getReg(0); } } else { - Handler.assignValueToReg(Args[i].Reg, VA.getLocReg(), VA); + Handler.assignValueToReg(ArgReg, VA.getLocReg(), VA); } } else if (VA.isMemLoc()) { MVT VT = MVT::getVT(Args[i].Ty); @@ -186,7 +192,7 @@ bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder, unsigned Offset = VA.getLocMemOffset(); MachinePointerInfo MPO; unsigned StackAddr = Handler.getStackAddress(Size, Offset, MPO); - Handler.assignValueToAddress(Args[i].Reg, StackAddr, Size, MPO, VA); + Handler.assignValueToAddress(ArgReg, StackAddr, Size, MPO, VA); } else { // FIXME: Support byvals and other weirdness return false; diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 2623b09834e..3a060b29c1b 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -1160,7 +1160,7 @@ bool IRTranslator::translateMemfunc(const CallInst &CI, return CLI->lowerCall(MIRBuilder, CI.getCallingConv(), MachineOperand::CreateES(Callee), - CallLowering::ArgInfo(0, CI.getType()), Args); + CallLowering::ArgInfo({0}, CI.getType()), Args); } void IRTranslator::getStackGuard(Register DstReg, |
