Add a hacky workaround for crashes due to vectors live across blocks.

Note that this code won't work for vectors that aren't legal on the
target.  Improvements coming.

llvm-svn: 26925

3 files changed, 31 insertions, 1 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index f2a8c8c1479..2744c415322 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -4262,6 +4262,9 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
 /// type for the result.
 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op, 
                                              MVT::ValueType NewVT) {
+  // FIXME: THIS IS A TEMPORARY HACK
+  if (Op.getValueType() == NewVT) return Op;
+  
   assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
   SDNode *Node = Op.Val;
   
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index a0ce3fb756e..8bf499eb7b5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1086,7 +1086,8 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
     break;
   case ISD::BIT_CONVERT:
     // Basic sanity checking.
-    assert(MVT::getSizeInBits(VT) == MVT::getSizeInBits(Operand.getValueType())
+    assert((Operand.getValueType() == MVT::Vector ||   // FIXME: This is a hack.
+           MVT::getSizeInBits(VT) == MVT::getSizeInBits(Operand.getValueType()))
            && "Cannot BIT_CONVERT between two different types!");
     if (VT == Operand.getValueType()) return Operand;  // noop conversion.
     if (OpOpcode == ISD::BIT_CONVERT)  // bitconv(bitconv(x)) -> bitconv(x)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 4107479bb53..d59184b1e5f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2285,6 +2285,32 @@ CopyValueToVirtualRegister(SelectionDAGLowering &SDL, Value *V, unsigned Reg) {
   SelectionDAG &DAG = SDL.DAG;
   if (SrcVT == DestVT) {
     return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
+  } else if (SrcVT == MVT::Vector) {
+    // FIXME: THIS DOES NOT SUPPORT PROMOTED/EXPANDED ELEMENTS!
+
+    // Figure out the right, legal destination reg to copy into.
+    const PackedType *PTy = cast<PackedType>(V->getType());
+    unsigned NumElts = PTy->getNumElements();
+    MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
+    
+    unsigned NumVectorRegs = 1;
+
+    // Divide the input until we get to a supported size.  This will always
+    // end with a scalar if the target doesn't support vectors.
+    while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
+      NumElts >>= 1;
+      NumVectorRegs <<= 1;
+    }
+    
+    MVT::ValueType VT;
+    if (NumElts == 1)
+      VT = EltTy;
+    else
+      VT = getVectorType(EltTy, NumElts);
+    
+    // FIXME: THIS ASSUMES THAT THE INPUT VECTOR WILL BE LEGAL!
+    Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
+    return DAG.getCopyToReg(SDL.getRoot(), Reg, Op);
   } else if (SrcVT < DestVT) {
     // The src value is promoted to the register.
     if (MVT::isFloatingPoint(SrcVT))