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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-04-22 20:21:36 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-04-22 20:21:36 +0000 |
| commit | 629d12de70959f49f0b8f78eb9e6e217103a24c7 (patch) | |
| tree | b4b1bfc0306ed7cbc5a790a87418dc1e473f3d7e /llvm/lib/CodeGen | |
| parent | 66ac1d61526268d1f81db8ed1d5caccfed2452ec (diff) | |
| download | bcm5719-llvm-629d12de70959f49f0b8f78eb9e6e217103a24c7.tar.gz bcm5719-llvm-629d12de70959f49f0b8f78eb9e6e217103a24c7.zip | |
DAGCombiner: Relax alignment restriction when changing load type
If the target allows the alignment, this should still be OK.
llvm-svn: 267209
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 6c9800824ef..690a53e785c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -7366,11 +7366,12 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) { (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)) && TLI.isLoadBitCastBeneficial(N0.getValueType(), VT)) { LoadSDNode *LN0 = cast<LoadSDNode>(N0); - unsigned Align = DAG.getDataLayout().getABITypeAlignment( - VT.getTypeForEVT(*DAG.getContext())); unsigned OrigAlign = LN0->getAlignment(); - if (Align <= OrigAlign) { + bool Fast = false; + if (TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT, + LN0->getAddressSpace(), OrigAlign, &Fast) && + Fast) { SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(), LN0->getPointerInfo(), LN0->isVolatile(), LN0->isNonTemporal(), |
