diff options
author | Peter Collingbourne <peter@pcc.me.uk> | 2016-10-09 04:38:57 +0000 |
---|---|---|
committer | Peter Collingbourne <peter@pcc.me.uk> | 2016-10-09 04:38:57 +0000 |
commit | 5c924d71173afc93aa0f0d115bd445a7496f4294 (patch) | |
tree | f8cc1da0f6670f2bfeeba7995953c724f1b14419 /llvm/lib/CodeGen | |
parent | e30cb00dc0d5a3ba4798c8da8f8535d069f49ddb (diff) | |
download | bcm5719-llvm-5c924d71173afc93aa0f0d115bd445a7496f4294.tar.gz bcm5719-llvm-5c924d71173afc93aa0f0d115bd445a7496f4294.zip |
Target: Remove unused entities.
llvm-svn: 283690
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r-- | llvm/lib/CodeGen/TargetInstrInfo.cpp | 29 | ||||
-rw-r--r-- | llvm/lib/CodeGen/TargetLoweringBase.cpp | 1 |
2 files changed, 0 insertions, 30 deletions
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp index 7ac2210ac52..4fdb6c54aa9 100644 --- a/llvm/lib/CodeGen/TargetInstrInfo.cpp +++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp @@ -1100,35 +1100,6 @@ int TargetInstrInfo::computeDefOperandLatency( return -1; } -unsigned TargetInstrInfo::computeOperandLatency( - const InstrItineraryData *ItinData, const MachineInstr &DefMI, - unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const { - - int DefLatency = computeDefOperandLatency(ItinData, DefMI); - if (DefLatency >= 0) - return DefLatency; - - assert(ItinData && !ItinData->isEmpty() && "computeDefOperandLatency fail"); - - int OperLatency = 0; - if (UseMI) - OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, *UseMI, UseIdx); - else { - unsigned DefClass = DefMI.getDesc().getSchedClass(); - OperLatency = ItinData->getOperandCycle(DefClass, DefIdx); - } - if (OperLatency >= 0) - return OperLatency; - - // No operand latency was found. - unsigned InstrLatency = getInstrLatency(ItinData, DefMI); - - // Expected latency is the max of the stage latency and itinerary props. - InstrLatency = std::max(InstrLatency, - defaultDefLatency(ItinData->SchedModel, DefMI)); - return InstrLatency; -} - bool TargetInstrInfo::getRegSequenceInputs( const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const { diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index 74ed7bc7331..187aa95d769 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -806,7 +806,6 @@ TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { = MaxStoresPerMemmoveOptSize = 4; UseUnderscoreSetJmp = false; UseUnderscoreLongJmp = false; - SelectIsExpensive = false; HasMultipleConditionRegisters = false; HasExtractBitsInsn = false; JumpIsExpensive = JumpIsExpensiveOverride; |