diff options
| author | Chris Lattner <sabre@nondot.org> | 2006-03-22 00:12:37 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-03-22 00:12:37 +0000 |
| commit | 5be4352124ad611b2b839124d64e4024bdbf429d (patch) | |
| tree | 876e5b0b30c8f73dfb4b856dc0d04ce08b4ecba2 /llvm/lib/CodeGen | |
| parent | baea59c61c5ba05370e63b7908e220431d6db7d6 (diff) | |
| download | bcm5719-llvm-5be4352124ad611b2b839124d64e4024bdbf429d.tar.gz bcm5719-llvm-5be4352124ad611b2b839124d64e4024bdbf429d.zip | |
Enclose some variables in a scope to avoid error with some gcc versions
llvm-svn: 26934
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 6c2b188b38f..5a1aef7a7d4 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -859,7 +859,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { } break; - case ISD::VEXTRACT_VECTOR_ELT: + case ISD::VEXTRACT_VECTOR_ELT: { // We know that operand #0 is the Vec vector. If the index is a constant // or if the invec is a supported hardware type, we can use it. Otherwise, // lower to a store then an indexed load. @@ -897,10 +897,11 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { // It's now an extract from the appropriate high or low part. Result = LegalizeOp(DAG.UpdateNodeOperands(Result, Tmp1, Tmp2)); } else { - // FIXME: IMPLEMENT STORE/LOAD lowering. + // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!! assert(0 && "unimp!"); } break; + } case ISD::CALLSEQ_START: { SDNode *CallEnd = FindCallEndFromCallStart(Node); |

