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| author | Dan Gohman <gohman@apple.com> | 2008-08-19 20:46:54 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-08-19 20:46:54 +0000 |
| commit | 547ce65467fdadc7cef160cb6d43c367d0bed02a (patch) | |
| tree | 00495de1f60e754f1bb591d0c430e073aeb7d37c /llvm/lib/CodeGen | |
| parent | c55fdcc9358d99bbc66bc6394a8490a7188fd74d (diff) | |
| download | bcm5719-llvm-547ce65467fdadc7cef160cb6d43c367d0bed02a.tar.gz bcm5719-llvm-547ce65467fdadc7cef160cb6d43c367d0bed02a.zip | |
Use the BuildMI overload that sets up a destination register
instead of the one that doesn't and then adding it manually.
llvm-svn: 55006
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp index 62fac06ceb8..5a7c8964750 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -70,10 +70,9 @@ unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass* RC) { MachineRegisterInfo &MRI = MF->getRegInfo(); const TargetInstrDesc &II = TII->get(MachineInstOpcode); - MachineInstr *MI = BuildMI(*MF, II); unsigned ResultReg = MRI.createVirtualRegister(RC); - MI->addOperand(MachineOperand::CreateReg(ResultReg, true)); + MachineInstr *MI = BuildMI(*MF, II, ResultReg); MBB->push_back(MI); return ResultReg; @@ -84,10 +83,9 @@ unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode, unsigned Op0) { MachineRegisterInfo &MRI = MF->getRegInfo(); const TargetInstrDesc &II = TII->get(MachineInstOpcode); - MachineInstr *MI = BuildMI(*MF, II); unsigned ResultReg = MRI.createVirtualRegister(RC); - MI->addOperand(MachineOperand::CreateReg(ResultReg, true)); + MachineInstr *MI = BuildMI(*MF, II, ResultReg); MI->addOperand(MachineOperand::CreateReg(Op0, false)); MBB->push_back(MI); @@ -99,10 +97,9 @@ unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode, unsigned Op0, unsigned Op1) { MachineRegisterInfo &MRI = MF->getRegInfo(); const TargetInstrDesc &II = TII->get(MachineInstOpcode); - MachineInstr *MI = BuildMI(*MF, II); unsigned ResultReg = MRI.createVirtualRegister(RC); - MI->addOperand(MachineOperand::CreateReg(ResultReg, true)); + MachineInstr *MI = BuildMI(*MF, II, ResultReg); MI->addOperand(MachineOperand::CreateReg(Op0, false)); MI->addOperand(MachineOperand::CreateReg(Op1, false)); |
