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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-31 23:41:23 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-31 23:41:23 +0000 |
| commit | 50d6579bac8fb6b9c65d3c762ab485804ffe3a9c (patch) | |
| tree | b03a213a83db64f2b48fd954567fc9c22f55bcea /llvm/lib/CodeGen | |
| parent | 886b7cc1073f316eb5e783e04d44c658bac2e318 (diff) | |
| download | bcm5719-llvm-50d6579bac8fb6b9c65d3c762ab485804ffe3a9c.tar.gz bcm5719-llvm-50d6579bac8fb6b9c65d3c762ab485804ffe3a9c.zip | |
GlobalISel: Fix MMO creation with non-power-of-2 mem size
It should probably just be mandatory for getTgtMemIntrinsic to return
the alignment.
llvm-svn: 352817
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 49a2262ea09..09bbbe2d8ae 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -1213,12 +1213,13 @@ bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) { TargetLowering::IntrinsicInfo Info; // TODO: Add a GlobalISel version of getTgtMemIntrinsic. if (TLI.getTgtMemIntrinsic(Info, CI, *MF, ID)) { - uint64_t Size = Info.memVT.getStoreSize(); - if (Info.align == 0) - Info.align = Size; + unsigned Align = Info.align; + if (Align == 0) + Align = DL->getABITypeAlignment(Info.memVT.getTypeForEVT(F->getContext())); + uint64_t Size = Info.memVT.getStoreSize(); MIB.addMemOperand(MF->getMachineMemOperand(MachinePointerInfo(Info.ptrVal), - Info.flags, Size, Info.align)); + Info.flags, Size, Align)); } return true; |
