[LegalizeVectorOps][X86] Enable expansion of vector fp_to_uint in LegalizeVectorOps to avoid scalarization.

The code here isn't great in all caess. Particularly v4f64->v4i32
on 64-bit AVX targets. But there is some improvement in some
configurations.

There's definitely some issues with computeNumSignBits with
X86ISD::STRICT_FCMP. As well as not being able to propagate sign
bits through merge_values nodes that get created during custom
legalization.

1 files changed, 5 insertions, 1 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 4127feda0e8..0975d2ad49d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -1178,13 +1178,15 @@ SDValue VectorLegalizer::ExpandFP_TO_UINT(SDValue Op) {
   // Attempt to expand using TargetLowering.
   SDValue Result, Chain;
   if (TLI.expandFP_TO_UINT(Op.getNode(), Result, Chain, DAG)) {
-    if (Op.getNode()->isStrictFPOpcode())
+    if (Op->isStrictFPOpcode())
       // Relink the chain
       DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Chain);
     return Result;
   }
 
   // Otherwise go ahead and unroll.
+  if (Op->isStrictFPOpcode())
+    return UnrollStrictFPOp(Op);
   return DAG.UnrollVectorOp(Op.getNode());
 }
 
@@ -1393,6 +1395,8 @@ SDValue VectorLegalizer::ExpandFixedPointMul(SDValue Op) {
 SDValue VectorLegalizer::ExpandStrictFPOp(SDValue Op) {
   if (Op.getOpcode() == ISD::STRICT_UINT_TO_FP)
     return ExpandUINT_TO_FLOAT(Op);
+  if (Op.getOpcode() == ISD::STRICT_FP_TO_UINT)
+    return ExpandFP_TO_UINT(Op);
 
   return UnrollStrictFPOp(Op);
 }