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| author | Sanjay Patel <spatel@rotateright.com> | 2018-10-15 18:05:34 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2018-10-15 18:05:34 +0000 |
| commit | 4cf1da0e021bbd05665e8dbc7eebb94a5f1ea461 (patch) | |
| tree | 99b69a862b411ccdda88867a301886f916a8f39c /llvm/lib/CodeGen | |
| parent | 4c9eb0fac4ee9e9a5dba13ea5b4bff3bfe4b2c12 (diff) | |
| download | bcm5719-llvm-4cf1da0e021bbd05665e8dbc7eebb94a5f1ea461.tar.gz bcm5719-llvm-4cf1da0e021bbd05665e8dbc7eebb94a5f1ea461.zip | |
[SelectionDAG] allow FP binops in SimplifyDemandedVectorElts
This is intended to make the backend on par with functionality that was
added to the IR version of SimplifyDemandedVectorElts in:
rL343727
...and the original motivation is that we need to improve demanded-vector-elements
in several ways to avoid problems that would be exposed in D51553.
Differential Revision: https://reviews.llvm.org/D52912
llvm-svn: 344541
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index d3a50788f79..150d22cffa7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1712,7 +1712,12 @@ bool TargetLowering::SimplifyDemandedVectorElts( break; } case ISD::ADD: - case ISD::SUB: { + case ISD::SUB: + case ISD::FADD: + case ISD::FSUB: + case ISD::FMUL: + case ISD::FDIV: + case ISD::FREM: { APInt SrcUndef, SrcZero; if (SimplifyDemandedVectorElts(Op.getOperand(1), DemandedElts, SrcUndef, SrcZero, TLO, Depth + 1)) |
