Fixed legalization of CONVERT_RNDSAT for integers.

llvm-svn: 59432

2 files changed, 16 insertions, 24 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index de1d94c72b0..fb05f334c09 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -280,35 +280,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
            CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
            CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
           "can only promote integers");
-  SDValue InOp = N->getOperand(0);
-
-  MVT InVT = InOp.getValueType();
   MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
-  switch (getTypeAction(InVT)) {
-  default:
-    assert(false && "Unknown type action!");
-    break;
-  case Legal:
-    break;
-  case PromoteInteger:
-    return DAG.getConvertRndSat(OutVT, GetPromotedInteger(InOp),
-                                N->getOperand(1), N->getOperand(2),
-                                N->getOperand(3), N->getOperand(4), CvtCode);
-    break;
-  case SoftenFloat:
-  case ExpandInteger:
-  case ExpandFloat:
-    break;
-  case ScalarizeVector:
-  case SplitVector:
-    assert(false && "can not convert a vector to a scalar!");
-  }
-  return DAG.getConvertRndSat(OutVT, InOp,
+  return DAG.getConvertRndSat(OutVT, N->getOperand(0),
                               N->getOperand(1), N->getOperand(2),
                               N->getOperand(3), N->getOperand(4), CvtCode);
 }
 
-
 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
   SDValue Op = GetPromotedInteger(N->getOperand(0));
   MVT OVT = N->getValueType(0);
@@ -632,6 +609,8 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
     case ISD::BRCOND:       Res = PromoteIntOp_BRCOND(N, OpNo); break;
     case ISD::BUILD_PAIR:   Res = PromoteIntOp_BUILD_PAIR(N); break;
     case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
+    case ISD::CONVERT_RNDSAT:
+                            Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
     case ISD::FP_EXTEND:    Res = PromoteIntOp_FP_EXTEND(N); break;
     case ISD::FP_ROUND:     Res = PromoteIntOp_FP_ROUND(N); break;
     case ISD::INSERT_VECTOR_ELT:
@@ -803,6 +782,18 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
   return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
 }
 
+SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
+  ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
+  assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
+           CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
+           CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
+           "can only promote integer arguments");
+  SDValue InOp = GetPromotedInteger(N->getOperand(0));
+  return DAG.getConvertRndSat(N->getValueType(0), InOp,
+                              N->getOperand(1), N->getOperand(2),
+                              N->getOperand(3), N->getOperand(4), CvtCode);
+}
+
 SDValue DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) {
   SDValue Op = GetPromotedInteger(N->getOperand(0));
   return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index ebba481902e..a96fbe187c6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -260,6 +260,7 @@ private:
   SDValue PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo);
   SDValue PromoteIntOp_BUILD_VECTOR(SDNode *N);
+  SDValue PromoteIntOp_CONVERT_RNDSAT(SDNode *N);
   SDValue PromoteIntOp_FP_EXTEND(SDNode *N);
   SDValue PromoteIntOp_FP_ROUND(SDNode *N);
   SDValue PromoteIntOp_INT_TO_FP(SDNode *N);