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authorZvi Rackover <zvi.rackover@intel.com>2017-03-15 19:48:36 +0000
committerZvi Rackover <zvi.rackover@intel.com>2017-03-15 19:48:36 +0000
commit48cdde0e59e152865ffdd460c817a1f1545d74ed (patch)
tree295b8ecb5808a78f7d5501b3d3cc590f0a579017 /llvm/lib/CodeGen
parent13f080fbebab4708afdaef542fda308d7a26a9c6 (diff)
downloadbcm5719-llvm-48cdde0e59e152865ffdd460c817a1f1545d74ed.tar.gz
bcm5719-llvm-48cdde0e59e152865ffdd460c817a1f1545d74ed.zip
[DAGCombine] Bail out if can't create a vector with at least two elements
Summary: Fixes pr32278 Reviewers: igorb, craig.topper, RKSimon, spatel, hfinkel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30978 llvm-svn: 297878
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp7
1 files changed, 5 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 0fe1edad7fc..2d6739ce085 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -14098,8 +14098,11 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
if (!SclTy.isFloatingPoint() && !SclTy.isInteger())
return SDValue();
- EVT NVT = EVT::getVectorVT(*DAG.getContext(), SclTy,
- VT.getSizeInBits() / SclTy.getSizeInBits());
+ unsigned VNTNumElms = VT.getSizeInBits() / SclTy.getSizeInBits();
+ if (VNTNumElms < 2)
+ return SDValue();
+
+ EVT NVT = EVT::getVectorVT(*DAG.getContext(), SclTy, VNTNumElms);
if (!TLI.isTypeLegal(NVT) || !TLI.isTypeLegal(Scalar.getValueType()))
return SDValue();
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