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authorBryan Chan <bryan.chan@huawei.com>2019-10-28 09:52:28 -0400
committerBryan Chan <bryan.chan@huawei.com>2019-10-28 09:56:39 -0400
commit35cb3ee4ca477095bb3dd74f60ab932e185be63f (patch)
tree04147bc1da778233770e54354fdffce2ce1f58c3 /llvm/lib/CodeGen
parentd2ec416c7babe65947ab841f9c9eb08844af3549 (diff)
downloadbcm5719-llvm-35cb3ee4ca477095bb3dd74f60ab932e185be63f.tar.gz
bcm5719-llvm-35cb3ee4ca477095bb3dd74f60ab932e185be63f.zip
[AArch64][Builtins] Avoid unnecessary cache cleaning
Use new control bits CTR_EL0.DIC and CTR_EL0.IDC to discover the d-cache cleaning and i-cache invalidation requirements for instruction-to-data coherence. This matches the behavior in the latest libgcc. Author: Shaokun Zhang <zhangshaokun@hisilicon.com> Reviewed By: peter.smith Differential Revision: https://reviews.llvm.org/D69247
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