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authorDuncan Sands <baldrick@free.fr>2009-09-06 08:33:48 +0000
committerDuncan Sands <baldrick@free.fr>2009-09-06 08:33:48 +0000
commit2fbeaf084ffe6467004d2a340336407c254f623f (patch)
treeb1689f01b10a49e9167d74b16da8d1aea0484196 /llvm/lib/CodeGen
parent109e762a5752e7a6bcee526bdbb6bbf1978152a7 (diff)
downloadbcm5719-llvm-2fbeaf084ffe6467004d2a340336407c254f623f.tar.gz
bcm5719-llvm-2fbeaf084ffe6467004d2a340336407c254f623f.zip
Remove some unused variables and methods warned about by
icc (#177, partial). Patch by Erick Tryzelaar. llvm-svn: 81106
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp3
-rw-r--r--llvm/lib/CodeGen/VirtRegRewriter.cpp3
2 files changed, 1 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 749170fb148..58f931234e1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4481,7 +4481,6 @@ SDValue DAGCombiner::visitBRCOND(SDNode *N) {
if (Op0.getOpcode() == ISD::AND &&
Op0.hasOneUse() &&
Op1.getOpcode() == ISD::Constant) {
- SDValue AndOp0 = Op0.getOperand(0);
SDValue AndOp1 = Op0.getOperand(1);
if (AndOp1.getOpcode() == ISD::Constant) {
@@ -5405,7 +5404,6 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
unsigned NumInScalars = N->getNumOperands();
EVT VT = N->getValueType(0);
- EVT EltType = VT.getVectorElementType();
// Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
// operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
@@ -5506,7 +5504,6 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
unsigned NumElts = VT.getVectorNumElements();
SDValue N0 = N->getOperand(0);
- SDValue N1 = N->getOperand(1);
assert(N0.getValueType().getVectorNumElements() == NumElts &&
"Vector shuffle must be normalized in DAG");
diff --git a/llvm/lib/CodeGen/VirtRegRewriter.cpp b/llvm/lib/CodeGen/VirtRegRewriter.cpp
index 79b366ca8d0..670e1cb575e 100644
--- a/llvm/lib/CodeGen/VirtRegRewriter.cpp
+++ b/llvm/lib/CodeGen/VirtRegRewriter.cpp
@@ -1128,8 +1128,7 @@ private:
return false;
// Back-schedule reloads and remats.
- MachineBasicBlock::iterator InsertLoc =
- ComputeReloadLoc(MII, MBB.begin(), PhysReg, TRI, false, SS, TII, MF);
+ ComputeReloadLoc(MII, MBB.begin(), PhysReg, TRI, false, SS, TII, MF);
// Load from SS to the spare physical register.
TII->loadRegFromStackSlot(MBB, MII, PhysReg, SS, RC);
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