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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-26 23:47:07 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-26 23:47:07 +0000 |
| commit | 26a6c74fbe7c9ecdc143ad916286240a7909f845 (patch) | |
| tree | fdedd53850a96c7b530b81481d32475339ef11f3 /llvm/lib/CodeGen | |
| parent | 4d47594fc543e35bfee20d3d92b3a62e7f619308 (diff) | |
| download | bcm5719-llvm-26a6c74fbe7c9ecdc143ad916286240a7909f845.tar.gz bcm5719-llvm-26a6c74fbe7c9ecdc143ad916286240a7909f845.zip | |
AMDGPU/GlobalISel: Legalize more bit ops
llvm-svn: 352295
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index bc7bd2b64cb..993f3bf6bd9 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -1395,6 +1395,9 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx, MI.eraseFromParent(); return Legalized; } + case TargetOpcode::G_AND: + case TargetOpcode::G_OR: + case TargetOpcode::G_XOR: case TargetOpcode::G_ADD: case TargetOpcode::G_SUB: case TargetOpcode::G_MUL: |
