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| author | Chris Lattner <sabre@nondot.org> | 2005-01-23 22:51:56 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-01-23 22:51:56 +0000 |
| commit | 24f0f0e28fb6f930522afe2bd310179969a209ac (patch) | |
| tree | e9dc5de4c25461b99b17e50fc1e87623e66faddd /llvm/lib/CodeGen | |
| parent | ae09d93b35fbb5203e25aee8f90c2c76c6697e57 (diff) | |
| download | bcm5719-llvm-24f0f0e28fb6f930522afe2bd310179969a209ac.tar.gz bcm5719-llvm-24f0f0e28fb6f930522afe2bd310179969a209ac.zip | |
Update this pass to set PhysRegsUsed info in MachineFunction.
llvm-svn: 19792
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/RegAllocLocal.cpp | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/RegAllocLocal.cpp b/llvm/lib/CodeGen/RegAllocLocal.cpp index 7d7ee64305e..d3c3277cbbf 100644 --- a/llvm/lib/CodeGen/RegAllocLocal.cpp +++ b/llvm/lib/CodeGen/RegAllocLocal.cpp @@ -38,6 +38,7 @@ namespace { MachineFunction *MF; const MRegisterInfo *RegInfo; LiveVariables *LV; + bool *PhysRegsEverUsed; // StackSlotForVirtReg - Maps virtual regs to the frame index where these // values are spilled. @@ -478,6 +479,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex); ++NumLoads; // Update statistics + PhysRegsEverUsed[PhysReg] = true; MI->SetMachineOperandReg(OpNum, PhysReg); // Assign the input register return MI; } @@ -547,6 +549,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { if (MO.isDef() && MO.isRegister() && MO.getReg() && MRegisterInfo::isPhysicalRegister(MO.getReg())) { unsigned Reg = MO.getReg(); + PhysRegsEverUsed[Reg] = true; spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in the reg PhysRegsUsed[Reg] = 0; // It is free and reserved now PhysRegsUseOrder.push_back(Reg); @@ -554,6 +557,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { *AliasSet; ++AliasSet) { PhysRegsUseOrder.push_back(*AliasSet); PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now + PhysRegsEverUsed[*AliasSet] = true; } } } @@ -565,16 +569,19 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { spillPhysReg(MBB, MI, Reg, true); PhysRegsUseOrder.push_back(Reg); PhysRegsUsed[Reg] = 0; // It is free and reserved now + PhysRegsEverUsed[Reg] = true; + for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); *AliasSet; ++AliasSet) { PhysRegsUseOrder.push_back(*AliasSet); PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now + PhysRegsEverUsed[*AliasSet] = true; } } // Okay, we have allocated all of the source operands and spilled any values // that would be destroyed by defs of this instruction. Loop over the - // implicit defs and assign them to a register, spilling incoming values if + // explicit defs and assign them to a register, spilling incoming values if // we need to scavenge a register. // for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { @@ -587,6 +594,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { // If DestVirtReg already has a value, use it. if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg))) DestPhysReg = getReg(MBB, MI, DestVirtReg); + PhysRegsEverUsed[DestPhysReg] = true; markVirtRegModified(DestVirtReg); MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register } @@ -652,6 +660,10 @@ bool RA::runOnMachineFunction(MachineFunction &Fn) { RegInfo = TM->getRegisterInfo(); LV = &getAnalysis<LiveVariables>(); + PhysRegsEverUsed = new bool[RegInfo->getNumRegs()]; + std::fill(PhysRegsEverUsed, PhysRegsEverUsed+RegInfo->getNumRegs(), false); + Fn.setUsedPhysRegs(PhysRegsEverUsed); + PhysRegsUsed.assign(RegInfo->getNumRegs(), -1); // initialize the virtual->physical register map to have a 'null' |

