summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen
diff options
context:
space:
mode:
authorDan Gohman <gohman@apple.com>2008-11-20 19:58:35 +0000
committerDan Gohman <gohman@apple.com>2008-11-20 19:58:35 +0000
commit22e9677a5e9ad5b596b1d2af339b37476767b10d (patch)
tree31d64f98b83889d5e5a73210c292e95a201ac4fa /llvm/lib/CodeGen
parent06613bc7de1ef3496081a2209745abf5883d2242 (diff)
downloadbcm5719-llvm-22e9677a5e9ad5b596b1d2af339b37476767b10d.tar.gz
bcm5719-llvm-22e9677a5e9ad5b596b1d2af339b37476767b10d.zip
Treat mid-block labels the same as terminators when building the
MachineInstr scheduling DAG, meaning they implicitly depend on all preceding defs. This fixes Benchmarks/Shootout-C++/except and Regression/C++/EH/simple_rethrow in -relocation-model=pic -disable-post-RA-scheduler=false mode. llvm-svn: 59747
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/ScheduleDAGInstrs.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index 72008c9c95f..b6bc44e849e 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -97,7 +97,7 @@ void ScheduleDAGInstrs::BuildSchedUnits() {
}
if (Terminator && SU->Succs.empty())
Terminator->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false);
- if (MI->getDesc().isTerminator())
+ if (MI->getDesc().isTerminator() || MI->isLabel())
Terminator = SU;
}
}
OpenPOWER on IntegriCloud