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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-27 00:52:51 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-27 00:52:51 +0000 |
commit | 211e89d4dd386334e3c20814ca99cbe1b9fc12cb (patch) | |
tree | 84d5c8ecc8a989d0cac2b03f711e65c5e4a42740 /llvm/lib/CodeGen | |
parent | 29ad802db08206000318b7445592abd620ccf650 (diff) | |
download | bcm5719-llvm-211e89d4dd386334e3c20814ca99cbe1b9fc12cb.tar.gz bcm5719-llvm-211e89d4dd386334e3c20814ca99cbe1b9fc12cb.zip |
GlobalISel: Implement narrowScalar for mul
llvm-svn: 352300
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r-- | llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index cf997a8926c..2ab35645064 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -343,6 +343,8 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, MI.eraseFromParent(); return Legalized; } + case TargetOpcode::G_MUL: + return narrowScalarMul(MI, TypeIdx, NarrowTy); case TargetOpcode::G_EXTRACT: { if (TypeIdx != 1) return UnableToLegalize; @@ -1527,6 +1529,51 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx, } LegalizerHelper::LegalizeResult +LegalizerHelper::narrowScalarMul(MachineInstr &MI, unsigned TypeIdx, LLT NewTy) { + unsigned DstReg = MI.getOperand(0).getReg(); + unsigned Src0 = MI.getOperand(1).getReg(); + unsigned Src1 = MI.getOperand(2).getReg(); + LLT Ty = MRI.getType(DstReg); + if (Ty.isVector()) + return UnableToLegalize; + + unsigned Size = Ty.getSizeInBits(); + unsigned NewSize = Size / 2; + if (Size != 2 * NewSize) + return UnableToLegalize; + + LLT HalfTy = LLT::scalar(NewSize); + // TODO: if HalfTy != NewTy, handle the breakdown all at once? + + unsigned ShiftAmt = MRI.createGenericVirtualRegister(Ty); + unsigned Lo = MRI.createGenericVirtualRegister(HalfTy); + unsigned Hi = MRI.createGenericVirtualRegister(HalfTy); + unsigned ExtLo = MRI.createGenericVirtualRegister(Ty); + unsigned ExtHi = MRI.createGenericVirtualRegister(Ty); + unsigned ShiftedHi = MRI.createGenericVirtualRegister(Ty); + + SmallVector<unsigned, 2> Src0Parts; + SmallVector<unsigned, 2> Src1Parts; + + extractParts(Src0, HalfTy, 2, Src0Parts); + extractParts(Src1, HalfTy, 2, Src1Parts); + + MIRBuilder.buildMul(Lo, Src0Parts[0], Src1Parts[0]); + + // TODO: Use smulh or umulh depending on what the target has. + MIRBuilder.buildUMulH(Hi, Src0Parts[1], Src1Parts[1]); + + MIRBuilder.buildConstant(ShiftAmt, NewSize); + MIRBuilder.buildAnyExt(ExtHi, Hi); + MIRBuilder.buildShl(ShiftedHi, ExtHi, ShiftAmt); + + MIRBuilder.buildZExt(ExtLo, Lo); + MIRBuilder.buildOr(DstReg, ExtLo, ShiftedHi); + MI.eraseFromParent(); + return Legalized; +} + +LegalizerHelper::LegalizeResult LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) { unsigned Opc = MI.getOpcode(); auto &TII = *MI.getMF()->getSubtarget().getInstrInfo(); |