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authorEli Friedman <eli.friedman@gmail.com>2009-08-19 08:46:10 +0000
committerEli Friedman <eli.friedman@gmail.com>2009-08-19 08:46:10 +0000
commit1e008c173a85c230e87df8f92b1e451806acaa29 (patch)
treea1ea674fd081ba443c835411fc59fedbe4dc855d /llvm/lib/CodeGen
parentd552be457a2f645f6b7875a79c161c18d096bfc1 (diff)
downloadbcm5719-llvm-1e008c173a85c230e87df8f92b1e451806acaa29.tar.gz
bcm5719-llvm-1e008c173a85c230e87df8f92b1e451806acaa29.zip
PR4737: Fix a nasty bug in load narrowing with non-power-of-two types.
llvm-svn: 79415
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 3c4f9de1cd9..4138e98f18e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3466,7 +3466,8 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
// Is the shift amount a multiple of size of VT?
if ((ShAmt & (EVTBits-1)) == 0) {
N0 = N0.getOperand(0);
- if (N0.getValueType().getSizeInBits() <= EVTBits)
+ // Is the load width a multiple of size of VT?
+ if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
return SDValue();
}
}
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