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author | Evan Cheng <evan.cheng@apple.com> | 2006-11-03 07:21:16 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2006-11-03 07:21:16 +0000 |
commit | 1dfd26a15128e42a497107a03d9c36581d7c015c (patch) | |
tree | f8922d32540063117bccd974fa0cdcfe126e7fff /llvm/lib/CodeGen | |
parent | 52f958741a086cb75e11d2a6922a08f579369a0a (diff) | |
download | bcm5719-llvm-1dfd26a15128e42a497107a03d9c36581d7c015c.tar.gz bcm5719-llvm-1dfd26a15128e42a497107a03d9c36581d7c015c.zip |
Rename
llvm-svn: 31413
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index b85a6b7c128..74e92218e5b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -187,7 +187,7 @@ namespace { SDOperand BasePtr; SDOperand Offset; ISD::MemOpAddrMode AM = ISD::UNINDEXED; - if (TLI.getLegalPreIndexedAddressBase(N, BasePtr, Offset, AM, DAG)) { + if (TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) { // Try turning it into a pre-indexed load / store except when // 1) Another use of base ptr is a predecessor of N. If ptr is folded // that would create a cycle. |