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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-23 17:58:48 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-05-23 17:58:48 +0000 |
| commit | 0f3ba44b57b0033a92a04530bcecd1b965adcd4b (patch) | |
| tree | e4c982a883a585536fb4665cd277ed63deca40da /llvm/lib/CodeGen | |
| parent | 9b2830b46e1c8fb1418956d8835d85225949e3c7 (diff) | |
| download | bcm5719-llvm-0f3ba44b57b0033a92a04530bcecd1b965adcd4b.tar.gz bcm5719-llvm-0f3ba44b57b0033a92a04530bcecd1b965adcd4b.zip | |
AMDGPU/GlobalISel: Legality for integer min/max
llvm-svn: 361519
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index aed1e4c590d..f9e8c835662 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -1083,6 +1083,8 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { case TargetOpcode::G_SDIV: case TargetOpcode::G_SREM: + case TargetOpcode::G_SMIN: + case TargetOpcode::G_SMAX: Observer.changingInstr(MI); widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); @@ -1111,6 +1113,8 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { return Legalized; case TargetOpcode::G_UDIV: case TargetOpcode::G_UREM: + case TargetOpcode::G_UMIN: + case TargetOpcode::G_UMAX: Observer.changingInstr(MI); widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); @@ -2207,6 +2211,10 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx, case G_FSQRT: case G_BSWAP: case G_SDIV: + case G_SMIN: + case G_SMAX: + case G_UMIN: + case G_UMAX: return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy); case G_SHL: case G_LSHR: @@ -2494,7 +2502,11 @@ LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx, } case TargetOpcode::G_AND: case TargetOpcode::G_OR: - case TargetOpcode::G_XOR: { + case TargetOpcode::G_XOR: + case TargetOpcode::G_SMIN: + case TargetOpcode::G_SMAX: + case TargetOpcode::G_UMIN: + case TargetOpcode::G_UMAX: { Observer.changingInstr(MI); moreElementsVectorSrc(MI, MoreTy, 1); moreElementsVectorSrc(MI, MoreTy, 2); |

