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| author | Sanjay Patel <spatel@rotateright.com> | 2018-10-07 15:32:06 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2018-10-07 15:32:06 +0000 |
| commit | 0b74c840ddb09c71e15bb383d0aad3526db5fe72 (patch) | |
| tree | bc9cd13ed0ad4fe651d0febdfe41c0bb336c8d29 /llvm/lib/CodeGen | |
| parent | 46a9dc2e3e2c687a43abbed253d0298fbcc67baa (diff) | |
| download | bcm5719-llvm-0b74c840ddb09c71e15bb383d0aad3526db5fe72.tar.gz bcm5719-llvm-0b74c840ddb09c71e15bb383d0aad3526db5fe72.zip | |
[DAGCombiner] allow undef elts in vector fabs/fneg matching
This change is proposed as a part of D44548, but we
need this independently to avoid regressions from improved
undef propagation in SimplifyDemandedVectorElts().
llvm-svn: 343940
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index c91aa83b421..bf3236cc69d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -9851,7 +9851,7 @@ static SDValue foldBitcastedFPLogic(SDNode *N, SelectionDAG &DAG, // Fold (bitcast int (and (bitcast fp X to int), 0x7fff...) to fp) -> fabs X // Fold (bitcast int (xor (bitcast fp X to int), 0x8000...) to fp) -> fneg X SDValue LogicOp0 = N0.getOperand(0); - ConstantSDNode *LogicOp1 = isConstOrConstSplat(N0.getOperand(1)); + ConstantSDNode *LogicOp1 = isConstOrConstSplat(N0.getOperand(1), true); if (LogicOp1 && LogicOp1->getAPIntValue() == SignMask && LogicOp0.getOpcode() == ISD::BITCAST && LogicOp0.getOperand(0).getValueType() == VT) |
