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authorTom Stellard <thomas.stellard@amd.com>2015-11-12 21:43:25 +0000
committerTom Stellard <thomas.stellard@amd.com>2015-11-12 21:43:25 +0000
commit0967c91e0cb6d57a3b5eabe4d671b0961f05ca18 (patch)
treeb9c264e6df7194e7b7f310c40f3d16bb09a95400 /llvm/lib/CodeGen
parent03fd3915ee43fb4206497a09b4150f2086e7933e (diff)
downloadbcm5719-llvm-0967c91e0cb6d57a3b5eabe4d671b0961f05ca18.tar.gz
bcm5719-llvm-0967c91e0cb6d57a3b5eabe4d671b0961f05ca18.zip
Revert "Remove unnecessary call to getAllocatableRegClass"
This reverts commit r252565. This also includes the revert of the commit mentioned below in order to avoid breaking tests in AMDGPU: Revert "AMDGPU: Set isAllocatable = 0 on VS_32/VS_64" This reverts commit r252674. llvm-svn: 252956
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp12
1 files changed, 4 insertions, 8 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index 5268da2ff4f..5ec10308dc2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -330,15 +330,11 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
// shrink VReg's register class within reason. For example, if VReg == GR32
// and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
if (II) {
- const TargetRegisterClass *OpRC = nullptr;
+ const TargetRegisterClass *DstRC = nullptr;
if (IIOpNum < II->getNumOperands())
- OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF);
-
- if (OpRC && !MRI->constrainRegClass(VReg, OpRC, MinRCSize)) {
- assert(OpRC->isAllocatable() &&
- "Constraining an allocatable VReg produced an unallocatable class?");
-
- unsigned NewVReg = MRI->createVirtualRegister(OpRC);
+ DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
+ if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
+ unsigned NewVReg = MRI->createVirtualRegister(DstRC);
BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
VReg = NewVReg;
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